Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Authors: 
Houji Zhou, Zhiwei Zhou, Shengguang Ren, Jia Chen, Yi Li, and Xiangshui MiaoAuthors Info & Claims
Houji Zhou, Zhiwei Zhou, Shengguang Ren, Jia Chen, Yi Li, and Xiangshui MiaoAuthors Info & ClaimsDecember 2023
Article No.: 7, Pages 1 - 6
Abstract
RRAM-enabled in-memory computing (IMC) is regarded as a promising solution for breaking the von Neumann bottleneck. Using RRAM-based IMC to construct heterogeneous computing systems can fully leverage the advantages of both digital and IMC platforms. Critical challenges are effectively managing the dataflows between the digital system and the analog IMC and providing a standard for communication. In this paper, from the perspective of hardware instruction execution, we designed a general RRAM-enabled analog instruction set architecture compatible with digital computing. These instructions adopted the vector-based computing concepts in RISC-V, and the examples compatible with RISC-V vector extension are demonstrated in detail. A tile-processing unit-array three-level architecture is also devolved to support the instruction execution. The hardware estimations are performed on 65 nm technology. Results indicate that the total activated power of the activated processing unit is 8.64 mW which is 4.9 times smaller than PUMA and 33.4 times smaller than ISAAC. The energy efficiency reaches 1190.7 GOPS/W, 1.42 × and 3.12 × compared with PUMA and ISAAC, respectively. Furthermore, as the analog and digital computing frequency increases, the peak energy efficiency can reach 40 TOPS/W which enables the future general use of the IMC-based heterogeneous system.
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Index Terms
- Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
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December 2023
222 pages
ISBN:9798400703256
DOI:10.1145/3611315
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Published: 25 January 2024
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NANOARCH '23
NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures
December 18 - 20, 2023
Dresden, Germany
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