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Accelerating RTL Simulation with Hardware-Software Co-Design

Authors:

Fares Elsabbagh,

Shabnam Sheikhha,

Victor A. Ying,

Quan M. Nguyen,

Daniel SanchezAuthors Info & Claims

MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 153 - 166

https://doi.org/10.1145/3613424.3614257

Published: 08 December 2023 Publication History

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Abstract

Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent.

We present ASH, a parallel architecture tailored to simulation workloads. ASH consists of a tightly codesigned hardware architecture and compiler for RTL simulation. ASH exploits two key opportunities. First, it performs dataflow execution of small tasks to leverage the fine-grained parallelism in simulation workloads. Second, it performs selective event-driven execution to run only the fraction of the design exercised each cycle, skipping ineffectual tasks. ASH hardware provides a novel combination of dataflow and speculative execution, and ASH’s compiler features several novel techniques to automatically leverage this hardware.

We evaluate ASH in simulation using large Verilog designs. An ASH chip with 256 simple cores is gmean 1,485 × faster than 1-core Verilator, and it is 32 × faster than parallel Verilator on a server CPU with 32 complex cores, while using 3 × less area.

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Cited By

Whangbo JLim EZhang CAnderson KGonzalez AGupta RKrishnakumar NKarandikar SNikolić BShao YAsanović K(2024)FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00044(501-515)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00044
Sabu ALiu CCarlson T(2024)Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core SimulationIEEE Access10.1109/ACCESS.2024.335406912(17669-17678)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3354069

Index Terms

Accelerating RTL Simulation with Hardware-Software Co-Design
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware
  1. Electronic design automation

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cover image ACM Conferences

MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture

October 2023

1528 pages

ISBN:9798400703294

DOI:10.1145/3613424

Copyright © 2023 Owner/Author.

This work is licensed under a Creative Commons Attribution-ShareAlike International 4.0 License.

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Published: 08 December 2023

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MICRO '23: 56th Annual IEEE/ACM International Symposium on Microarchitecture

October 28 - November 1, 2023

ON, Toronto, Canada

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Cited By

Whangbo JLim EZhang CAnderson KGonzalez AGupta RKrishnakumar NKarandikar SNikolić BShao YAsanović K(2024)FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00044(501-515)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00044
Sabu ALiu CCarlson T(2024)Viper: Utilizing Hierarchical Program Structure to Accelerate Multi-Core SimulationIEEE Access10.1109/ACCESS.2024.335406912(17669-17678)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3354069

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