A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors
Authors: 
Marco Siracusa, Víctor Soria-Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià ArmejachAuthors Info & Claims
Marco Siracusa, Víctor Soria-Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià ArmejachAuthors Info & ClaimsPages 1332 - 1346
Abstract
This paper proposes the Tensor Marshaling Unit (TMU), a near-core programmable dataflow engine for multicore architectures that accelerates tensor traversals and merging, the most critical operations of sparse tensor workloads running on today’s computing infrastructures. The TMU leverages a novel multi-lane design that enables parallel tensor loading and merging, which naturally produces vector operands that are marshaled into the core for efficient SIMD computation. The TMU supports all the necessary primitives to be tensor-format and tensor-algebra complete. We evaluate the TMU on a simulated multicore system using a broad set of tensor algebra workloads, achieving 3.6 ×, 2.8 ×, and 4.9 × speedups over memory-intensive, compute-intensive, and merge-intensive vectorized software implementations, respectively.
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Index Terms
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DOI:10.1145/3613424
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Association for Computing Machinery
New York, NY, United States
Publication History
Published: 08 December 2023
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- Research-article
- Research
- Refereed limited
Conference
MICRO '23
Sponsor:
MICRO '23: 56th Annual IEEE/ACM International Symposium on Microarchitecture
October 28 - November 1, 2023
ON, Toronto, Canada
Acceptance Rates
Overall Acceptance Rate 484 of 2,242 submissions, 22%
Upcoming Conference
MICRO '24
- Sponsor:
- sigmicro
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