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The effect of instruction set complexity on program size and memory performance

Authors:

Jack W. Davidson,

Richard A. VaughanAuthors Info & Claims

ACM SIGPLAN Notices, Volume 22, Issue 10

Pages 60 - 64

https://doi.org/10.1145/36205.36184

Published: 01 October 1987 Publication History

Abstract

One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require more instructions to implement the same function. In addition, the tendency of RISC machines to use fixed length instructions with a few instruction formats also increases object program size. It has been conjectured that the resulting larger programs could adversely affect memory performance and bus traffic. In this paper we report the results of a set of experiments to isolate and determine the effect of instruction set complexity on cache memory performance and bus traffic. Three high-level language compilers were constructed for machines with instruction sets of varying degrees of complexity. Using a set of benchmark programs, we evaluated the effect of instruction set complexity had on program size. Five of the programs were used to perform a set of trace-driven simulations to study each machine's cache and bus performance. While we found that the miss ratio is affected by object program size, it appears that this can be corrected by simplying increasing the size of the cache. Our measurements of bus traffic, however, show that even with large caches, machines with simple instruction sets can expect substantially more main memory reads than machines with dense object programs.

References

[1]

Auslander, M. and Hopkins, M., An Overview of the PL.8 Compiler, Proceedings of the ACM SIGPLAN Notices '82 Symposium on Compiler Construction, Boston, MA, June 1982, 22--31.

Digital Library

[2]

Colwell, R. P., III, C. Y. H., Jensen, E. D., Sprunt, H. M. B. and Kollar, C. P., Computers, Complexity, and Controversy, IEEE Computer 18, 9 (September 1985), 8--19.

Digital Library

[3]

Davidson, J. W. and Fraser, C. W., Register Allocation and Exhaustive Peephole Optimization, Software---Practice and Experience 14, 9 (September 1984), 857--866.

[4]

Davidson, J. W. and Fraser, C. W., Code Selection through Object Code Optimization, Transactions on Programming Languages and System 6, 4 (October 1984), 7--32.

Digital Library

[5]

Davidson, J. W., A Retargetable instruction Reorganizer, Proceedings of the SIGPLAN Notices '86 Symposium on Compiler Construction, Palo Alto, CA, June 1986, 234--241.

Digital Library

[6]

Emer, J. S. and Clark, D. W., A Characterization of Processor Performance in the VAX-11/780, Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, June 1984, 301--310.

Digital Library

[7]

Hanson, D. R., The Y Programming Language, SIGPLAN Notices 16, 2 (February 1981), 59--68.

Digital Library

[8]

Hennessy, J. L., VLSI Processor Architecture, IEEE Transactions on Computers 33, 12 (December 1984), 1221--1246.

[9]

Johnson, S. C., A Tour Through the Portable C. Compiler, Unix Programmer's Manual, 7th Edition 2B, (January 1979), Section 33.

[10]

Kernighan, B. W. and Plauger, P. J., Software Tools, Addison-Wesley, Reading, MA, 1976.

Digital Library

[11]

Leverett, B. W., Cattell, R. G. G., Hobbs, S. O., Newcomer, J. M., Reiner, A. H., Schatz, B. R. and Wulf, W. A., An Overview of the Production Quality Compiler-Compiler Project, CMUCS-79-105, Carnegie-Mellon University, Pittsburg, PA, February 1979.

[12]

Patterson, D. A. and Ditzel, D. R., The Case for the Reduced Instruction Set Computer, Computer Architecture News 8, 6 (October 1980), 25--33.

Digital Library

[13]

Patterson, D. A. and Sequin, C. H., RISC I: A Reduced Instruction Set VLSI Computer, Proceedings of the Eighth Annual Symposium on Computer Architecture, Minneapolis, MN, May 1981, 443--457.

Digital Library

[14]

Patterson, D. A., Reduced Instruction Set Computers, Communications of the ACM 28, 1 (January 1985), 8--21.

Digital Library

[15]

Radin, G., The 801 Minicomputer, Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, CA, March 1982, 39--47.

Digital Library

[16]

Rymarczyk, J. W., Coding Guidelines for Pipelined Processors, Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, CA, March 1982, 12--19.

Digital Library

[17]

Schatz, B. R., Algorithms for Optimizing Transformations in a General Purpose Compiler: Propagation and Renaming, RC 6232, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, October 1976.

[18]

Sethi, R. and Ullman, J. D., The Generation of Optimal Code for Arithmetic Expressions, Journal of the ACM 17, 6 (October 1970), 715--728.

Digital Library

[19]

Smith, A. J., Cache Memories, Computing Surveys 14, 3 (September 1982), 473--530.

Digital Library

[20]

Tanenbaum, A. S., Implications of Structured Programming for Machine Architecture, Communications of the ACM 21, 3 (March 1978), 237--246.

Digital Library

Cited By

Lozano HIto M(2016)Increasing the Code Density of Embedded RISC Applications2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.33(182-189)Online publication date: May-2016
https://doi.org/10.1109/ISORC.2016.33
Pettis KHansen RDavidson J(2004)Profile guided code positioningACM SIGPLAN Notices10.1145/989393.98943339:4(398-411)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1145/989393.989433
Chen WChang PConte THwu W(1993)The Effect of Code Expanding Optimizations on Instruction Cache DesignIEEE Transactions on Computers10.1109/12.24159442:9(1045-1057)Online publication date: 1-Sep-1993
https://dl.acm.org/doi/10.1109/12.241594
Show More Cited By

Index Terms

The effect of instruction set complexity on program size and memory performance
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

Recommendations

The effect of instruction set complexity on program size and memory performance
ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require ...
The effect of instruction set complexity on program size and memory performance

One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require ...
The effect of instruction set complexity on program size and memory performance

One potential disadvantage of a machine with a reduced instruction set is that object programs may be substantially larger than those for a machine with a richer, more complex instruction set. The main reason is that a small instruction set will require ...

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 22, Issue 10

Oct. 1987

189 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/36205

Editor:
Randy Katz
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems
October 1987
205 pages
ISBN:0818608056
DOI:10.1145/36206
Editor:
Randy Katz
Univ. of California, Berkeley
,
General Chair:
Martin Freeman
Stanford University and Philips/Signetics

Copyright © 1987 Copyright is held by the owner/author(s).

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 1987

Published in SIGPLAN Volume 22, Issue 10

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Cited By

Lozano HIto M(2016)Increasing the Code Density of Embedded RISC Applications2016 IEEE 19th International Symposium on Real-Time Distributed Computing (ISORC)10.1109/ISORC.2016.33(182-189)Online publication date: May-2016
https://doi.org/10.1109/ISORC.2016.33
Pettis KHansen RDavidson J(2004)Profile guided code positioningACM SIGPLAN Notices10.1145/989393.98943339:4(398-411)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1145/989393.989433
Chen WChang PConte THwu W(1993)The Effect of Code Expanding Optimizations on Instruction Cache DesignIEEE Transactions on Computers10.1109/12.24159442:9(1045-1057)Online publication date: 1-Sep-1993
https://dl.acm.org/doi/10.1109/12.241594
Mitchell CFlynn M(1990)The effects of processor architecture on instruction memory trafficACM Transactions on Computer Systems10.1145/99926.999338:3(230-250)Online publication date: 1-Aug-1990
https://dl.acm.org/doi/10.1145/99926.99933
Pettis KHansen R(1990)Profile guided code positioningACM SIGPLAN Notices10.1145/93548.9355025:6(16-27)Online publication date: 1-Jun-1990
https://dl.acm.org/doi/10.1145/93548.93550
Steenkiste P(1989)The impact of code density on instruction cache performanceACM SIGARCH Computer Architecture News10.1145/74926.7495417:3(252-259)Online publication date: 1-Apr-1989
https://dl.acm.org/doi/10.1145/74926.74954
Debaere E(1989)Instruction-path coprocessing to solve some RISC problemsACM SIGARCH Computer Architecture News10.1145/71302.7131217:5(83-94)Online publication date: 1-Sep-1989
https://dl.acm.org/doi/10.1145/71302.71312
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