research-article

Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2

Authors:

Nadia El Mrabet,

Pascal VeronAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems, Volume 17, Issue 1

Article No.: 9, Pages 1 - 31

https://doi.org/10.1145/3624571

Published: 27 January 2024 Publication History

Abstract

This article describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic architectures result in parallelized, DSP48E2-optimized scheduling of operations analogous to the FIOS block variant of the Montgomery Multiplication. We explore the impacts of different pipelining strategies within DSP blocks, scheduling of operations, processing element configurations, global design structures and their tradeoffs in terms of performance and resource costs. We discuss the application of our methodology to multiple types of DSP primitives. We provide ready-to-use fast, efficient, and fully parametrizable designs, which can adapt to a wide range of requirements and applications. Implementations are scalable to any operand width. Our most efficient designs can perform 128, 256, 512, 1024, 2048, and 4096 bits Montgomery modular multiplications in 0.0992 μs, 0.2032 μs, 0.3952 μs, 0.7792μs, 1.550 μs, and 3.099 μs using 4, 6, 11, 21, 41, and 82 DSP blocks, respectively.

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Cited By

Sakamoto JFujimoto DAnzai RYoshida NMatsumoto T(2024)High-Throughput Bilinear Pairing Processor for Server-Side FPGA ApplicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.340216432:8(1498-1511)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3402164

Index Terms

Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 17, Issue 1

March 2024

446 pages

EISSN:1936-7414

DOI:10.1145/3613534

Editor:
Deming Chen
University of Illinois, Urbana-Champaign, USA

Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 27 January 2024

Online AM: 15 September 2023

Accepted: 04 September 2023

Revised: 23 August 2023

Received: 17 February 2023

Published in TRETS Volume 17, Issue 1

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Cited By

Sakamoto JFujimoto DAnzai RYoshida NMatsumoto T(2024)High-Throughput Bilinear Pairing Processor for Server-Side FPGA ApplicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.340216432:8(1498-1511)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3402164

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