Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
Pages 211 - 222
Abstract
Field-programmable gate arrays (FPGAs) provide opportunities for adopting cutting-edge microarchitectural technologies to accelerate emerging applications. However, it remains challenging to program FPGAs. On one hand, hardware description languages (HDLs), although lauded for their ability to provide circuit representations that closely mimic the inherent hardware structures, have been criticized for their inherent shortcomings, including low-level programming and poor productivity. On the other hand, high-level synthesis (HLS) attempts to raise the abstraction level of hardware design to the software domain. However, it often results in unpredictable solutions due to semantic difference between software and hardware. Furthermore, domain-specific languages (DSLs) tailored for FPGA programming have their own set of limitations, particularly in terms of expressiveness and flexibility. In this work, we introduce a novel hardware design framework named Cement \xspace, which encompasses the embedded HDL (eHDL) CmtHDL \xspace and the compiler CmtC \xspace, providing a better programming framework for FPGA. CmtHDL \xspace introduces event-based procedural specification alongside RTL description, empowering designers to describe hardware productively at a higher level of abstraction while maintaining cycle-deterministic behavior. CmtC \xspace provides a comprehensive compilation workflow that includes analyzing the timing behavior of the hardware and conducting synthesis to yield solutions with anticipated performance for FPGAs. Experiments show that Cement \xspace provides comparable productivity, but offers 1.41\texttimes-3.49\texttimes\xspace speedup, and saves 23%-82% resources compared to existing HLS or DSL tools. The practical significance of Cement \xspace is further validated through a case study of designing real-world FPGA-based accelerators.
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Index Terms
- Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis
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