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RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model

Published: 07 November 2024 Publication History

Abstract

This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities, our analysis indicates that approximately 55% of errors in LLM-generated Verilog are syntax-related, leading to compilation failures. To tackle this issue, we introduce a novel debugging framework that employs Retrieval-Augmented Generation (RAG) and ReAct prompting, enabling LLMs to act as autonomous agents in interactively debugging the code with feedback. This framework demonstrates exceptional proficiency in resolving syntax errors, successfully correcting about 98.5% of compilation errors in our debugging dataset, comprising 212 erroneous implementations derived from the VerilogEval benchmark. Our method leads to 32.3% and 10.1% increase in pass@1 success rates in the VerilogEval-Machine and VerilogEval-Human benchmarks, respectively. The source code and benchmark are available at https://github.com/NVlabs/RTLFixer.

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cover image ACM Conferences
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
June 2024
2159 pages
ISBN:9798400706011
DOI:10.1145/3649329
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 07 November 2024

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DAC '24: 61st ACM/IEEE Design Automation Conference
June 23 - 27, 2024
CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2025)EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA ToolsACM Transactions on Design Automation of Electronic Systems10.1145/3715326Online publication date: 27-Jan-2025
  • (2025)Architecture 2.0: Foundations of Artificial Intelligence Agents for Modern Computer System DesignComputer10.1109/MC.2024.352164158:2(116-124)Online publication date: Feb-2025
  • (2024)Navigating SoC Security Landscape on LLM-Guided PathsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660393(252-257)Online publication date: 12-Jun-2024
  • (2024)Evolutionary Large Language Models for Hardware Security: A Comparative SurveyProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3660390(496-501)Online publication date: 12-Jun-2024
  • (2024)SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)10.1109/PAINE62042.2024.10792717(1-7)Online publication date: 12-Nov-2024
  • (2024)Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740262(1-9)Online publication date: 9-Sep-2024
  • (2024)OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740242(1-7)Online publication date: 9-Sep-2024
  • (2024)EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691774(1-5)Online publication date: 28-Jun-2024
  • (2024)The potential of LLMs in hardware designJournal of Engineering Research10.1016/j.jer.2024.08.001Online publication date: Aug-2024

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