Learned Index Acceleration with FPGAs: A SMART Approach

Indexes in database systems such as B+trees and hash tables are designed for fast data retrieval. These are created on columns of a table and serve as a pointer to map a key to the position of a record on a table. Much research has been conducted on topics related to the faster index. A learned index is one such area of study. Learned index approaches can achieve significant performance improvement over traditional indexing techniques. However, query performance with learned indexes is limited by the constraints imposed by the CPU architecture. FPGAs, on the other hand, offer a suitable alternative by offering energy efficiency and potentially better performance. This paper proposes a new methodology that considers the advantages of the learned index and FPGAs. This methodology is called the Selective Mathematical Operation AcceleRaTion (SMART) approach with an FPGA for an end-to-end acceleration of learned indexes. Being a hybrid between a CPU approach and an FPGA approach, the SMART model of index acceleration achieves higher throughput than the CPU-based implementation while maintaining the data structure storage on the CPU. Our SMART approach accelerated the radix spline (RS) learned index using a single FPGA without any off-chip memory resources. The resulting index, called SMART-RS, achieves an overall speedup of 5.5 × as compared to a CPU-based RS index on the SOSD benchmark datasets.