FPIA: Field-Programmable Ising Arrays with In-Memory Computing
Authors: 
George Higgins Hutchinson, Ethan Sifferman, Tinish Bhattacharya, Dongseok Kwon, Dmitri B StrukovAuthors Info & Claims
George Higgins Hutchinson, Ethan Sifferman, Tinish Bhattacharya, Dongseok Kwon, Dmitri B StrukovAuthors Info & ClaimsPages 1 - 6
Abstract
Ising Machines, a promising approach for solving combinatorial optimization problems, are naturally suited for energy-saving and compact in-memory computing implementations with emerging memories. A naïve in-memory computing implementation of a quadratic Ising Machine requires an array of coupling weights that grows quadratically with problem size. This approach, however, uses resources inefficiently due to the inherent sparsity of practical optimization problems. We first show that this issue can be addressed by partitioning a coupling array into smaller sub-arrays. This technique, however, requires interconnecting sub-arrays, which incurs overhead. In response, we present FPIA, an in-memory computing architecture for quadratic Ising Machines inspired by island-type field programmable gate arrays. We adapt open-source tools to optimize problem embedding and model overhead. Modeling results of benchmark problems for the developed architecture show up to 10x increase in density and speed compared to the baseline approach. Finally, we discuss algorithm/circuit co-design techniques for further improvements.
References
[1]
S. Agarwal, S.J. Plimpton, D.R. Hughart, et al. 2016. Resistive memory device requirements for a neural algorithm accelerator. In IJCNN. 929--938.
[2]
T. Balyo, N. Froleyks, M.J.H. Heule, et al. 2020. Proceedings of SAT Competition 2020 : Solver and Benchmark Descriptions. http://hdl.handle.net/10138/318450
[3]
T. Balyo, M.J.H. Heule, and M. Järvisalo. 2017. Proceedings of SAT Competition 2017 : Solver and Benchmark Descriptions. http://hdl.handle.net/10138/224324
[4]
M. Bavandpour, M.R. Mahmoodi, and D.B. Strukov. 2020. aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator. IEEE JXCDC 6, 1 (2020), 98--106.
[5]
V. Betz and J. Rose. 1997. VPR: a new packing, placement and routing tool for FPGA research. Lecture Notes in Computer Science, Vol. 1304. Springer Berlin Heidelberg, Berlin, Heidelberg, 213--222.
[6]
V. Betz, J. Rose, and A. Marquardt. 1999. Architecture and CAD for Deep-Submicron FPGAS. Springer US, Boston, MA.
[7]
K.Y. Camsari, R. Faria, B.M. Sutton, and S. Datta. 2017. Stochastic p-bits for Invertible Logic. Phys. Rev. X 7, 3 (2017), 031014.
[8]
F. Glover, G. Kochenberger, and Y. Du. 2019. Quantum Bridge Analytics I: a tutorial on formulating and using QUBO models. 4OR 17, 4 (2019), 335--371.
[9]
X. Guo, F. Merrikh-Bayat, M. Prezioso, et al. 2017. Temperature-Insensitive Analog Vector-by-Matrix Multiplier Based on 55 nm NOR Flash Memory Cells. In IEEE CICC. 1--4.
[10]
M. Hizzani, A. Heittmann, G. Hutchinson, et al. 2023. Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines. arXiv:2311.01171
[11]
H. H. Hoos. 2011. SATLIB --- Benchmark Problems. https://www.cs.ubc.ca/~hoos/SATLIB/benchm.html
[12]
H. H. Hoos and Thomas Stützle. 2005. Stochastic local search: foundations and applications. Morgan Kaufmann Publishers, San Francisco, CA.
[13]
J.J. Hopfield. 1982. Neural networks and physical systems with emergent collective computational abilities. PNAS 79, 8 (1982), 2554--2558.
[14]
F. Hutter, H.H. Hoos, and K. Leyton-Brown. 2011. Sequential Model-Based Optimization for General Algorithm Configuration. Lecture Notes in Computer Science, Vol. 6683. Springer Berlin Heidelberg, Berlin, Heidelberg, 507--523.
[15]
T. Izumi, T. Yokomaru, A. Takahashi, and Y. Kajitani. 1998. Computational complexity analysis of set-bin-packing problem. In ISCAS, Vol. 6. IEEE, Monterey, CA, USA, 244--247.
[16]
A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy. 2019. 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing. IEEE TVLSI 27, 11 (2019), 2556--2567.
[17]
L. Kull, T. Toifl, M. Schmatz, et al. 2013. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE JSSC 48, 12 (2013), 3049--3058.
[18]
I. Kuon and J. Rose. 2008. iFAR - intelligent FPGA Architecture Repository. https://www.eecg.utoronto.ca/vpr/architectures/
[19]
M. Lindauer, K. Eggensperger, M. Feurer, et al. 2022. SMAC3: A versatile bayesian optimization package for hyperparameter optimization. JMLR 23, 54 (2022), 1--9. https://www.jmlr.org/papers/v23/21-0888.html
[20]
A. Lu, J. Hur, Y.-C. Luo, et al. 2023. Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 13, 1 (2023), 422--435.
[21]
A. Lucas. 2014. Ising formulations of many NP problems. Frontiers in Physics 2 (2014).
[22]
J. Luu, I. Kuon, P. Jamieson, et al. 2009. VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. ACM, Monterey California USA, 133--142.
[23]
S. Mittal, J.S. Vetter, and D. Li. 2015. A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches. IEEE Transactions on Parallel and Distributed Systems 26, 6 (2015), 1524--1537.
[24]
N. Mohseni, P. McMahon, and T. Byrnes. 2022. Ising machines as hardware solvers of combinatorial optimization problems. Nature Reviews Physics 3 (04 2022), 363--379.
[25]
A. Mondal and A. Srivastava. 2021. Ising-FPGA: A Spintronics-based Reconfigurable Ising Model Solver. ACM Transactions on Design Automation of Electronic Systems 26, 1 (2021), 1--27.
[26]
M. Nazm Bojnordi and E. Ipek. 2016. Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning. In HPCA'16. 1--13.
[27]
P. Purdom and A. Sabry. 2018. CNF Generator for Factoring Problems. https://cgi.luddy.indiana.edu/~sabry/cnf.html
[28]
K. Roy and M. Mehendale. 1992. Optimization of channel segmentation for channeled architecture FPGAs. In IEEE CICC. 4--4.
[29]
A. Sebastian, M. Le Gallo, R. Khaddam-Aljameh, and E. Eleftheriou. 2020. Memory devices and applications for in-memory computing. Nature Nanotechnology 15 (2020), 529--544.
[30]
T. Sejnowski. 1987. Higher-Order Boltzmann Machines. 151 (Mar 1987).
[31]
A. Shafiee, A. Nag, N. Muralimanohar, et al. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. In ACM/IEEE ISCA. 14--26.
[32]
A. Sharma, R. Afoakwa, A. Ignjatovic, and M. C. Huang. 2022. Increasing Ising Machine Capacity with Multi-Chip Architectures. In ACM ISCA'22. 508--521.
[33]
R. Tessier and H. Giza. 2000. Balancing Logic Utilization and Area Efficiency in FPGAs. In Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (Lecture Notes in Computer Science), R.W. Hartenstein and H. Grünbacher (Eds.). Springer, Berlin, Heidelberg, 535--544.
[34]
D. Wang, X. Zhu, X. Guo, et al. 2019. A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology. MDPI Electronics 8, 33 (2019), 305.
[35]
H. Wei, P. Zhang, B. Datta Sahoo, and B. Razavi. 2013. An 8-Bit 4-GS/s 120-mW CMOS ADC. In IEEE CICC. 1--4.
[36]
C. Yu, T. Yoo, Tony T.-H. Kim, et al. 2020. A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC. In IEEE CICC. 1--4.
Index Terms
- FPIA: Field-Programmable Ising Arrays with In-Memory Computing
Recommendations
Reconfigurable Processing With Field Programmable Gate Arrays
ASAP '96: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and ProcessorsIn-system-programmable, SRAM-based Field Programmable Gate Arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting ...
Comments
Information & Contributors
Information
Published In
August 2024
384 pages
ISBN:9798400706882
DOI:10.1145/3665314
- Chair:
- Pascal Meinerzhagen,
- Program Chair:
- Kapil Dev,
- Program Co-chair:
- Jerald Yoo
This work is licensed under a Creative Commons Attribution-NonCommercial International 4.0 License.
Sponsors
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE CAS
- IEEE EDA
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 09 September 2024
Check for updates
Author Tags
Qualifiers
- Research-article
Funding Sources
Conference
ISLPED '24
Sponsor:
ISLPED '24: 29th ACM/IEEE International Symposium on Low Power Electronics and Design
August 5 - 7, 2024
CA, Newport Beach, USA
Acceptance Rates
Overall Acceptance Rate 398 of 1,159 submissions, 34%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 171Total Downloads
- Downloads (Last 12 months)171
- Downloads (Last 6 weeks)50
Reflects downloads up to 13 Jan 2025
Other Metrics
Citations
Cited By
View allView Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in