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Usage-based characterization of complex functional blocks for reuse in behavioral synthesis

Authors:

Nong Fan,

Viraphol Chaiyakul,

Daniel D. GajskiAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 43 - 48

https://doi.org/10.1145/368434.368508

Published: 28 January 2000 Publication History

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References

[1]

P. Jha and N. Dutt, "Design reuse through high-level mapping," Proc. of European Design & Test Conference, 1995.

Digital Library

Google Scholar

[2]

L. Ramachandran and D. Gajski, "Behavioral design assistant (BdA) user's manual: version 1.0," University of California, Irvine, Dept. of Information and Computer Science, Technical report, 94-36.

Google Scholar

[3]

T. Ly, D. Knapp, R. Miller and D. MacMillen, "Scheduling using behavioral templates," Proc. of DAC, 1995.

Digital Library

Google Scholar

[4]

B. Landwehr, P. Marwedel and R. Domer, "OSCAR: optimum simultaneous scheduling allocation and resource binding based on integer programming," Proc. of EURO-VHDL, 1994.

Google Scholar

[5]

W. Geurts, F. Catthoor and H. De Man, "Quadratic zero-one programming-based synthesis of application-specific data paths," IEEE Transactions on CAD, vol. 14, pp. 1-11, 1995.

Digital Library

Google Scholar

[6]

O. Bringmann and W. Rosenstiel, "Resource sharing in hierarchical synthesis," International Conference on Computer-Aided Design, 1997.

Digital Library

Google Scholar

[7]

P. Kission, H.Ding and A. Jerraya, "VHDL based design methodology for hierarchy and component re-use," Proc. EURO-VHDL, 1995.

Digital Library

Google Scholar

[8]

J. S. Sun and R. W. Brodersen, "Design of system interface modules," Proc. ICCAD, 1992.

Digital Library

Google Scholar

[9]

D. Gajski, N. Dutt, A. Wu and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.

Digital Library

Google Scholar

[10]

H. Juan, Design Methodology and Algorithms for Interactive Behavioral Synthesis, Ph.D. Dissertation, University of California, Irvine, 1997.

Digital Library

Google Scholar

[11]

P.M. Embree and B. Kimble, C Language Algorithms for Digital Signal Processing, Prentice Hall, 1991.

Digital Library

Google Scholar

[12]

http://WWW.ERC.MsState.Edu/mpl/scmos/html/ release.html

Google Scholar

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Lhairech-Lebreton GCoussy PMartin E(2010)Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGAProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.94(464-468)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.1109/FPL.2010.94
Sllame A(2004)A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology4th IEEE International Workshop on System-on-Chip for Real-Time Applications10.1109/IWSOC.2004.1319895(287-290)Online publication date: 2004
https://doi.org/10.1109/IWSOC.2004.1319895

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DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. The optimizations exploit the high-...

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ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 January 2000

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Lhairech-Lebreton GCoussy PMartin E(2010)Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGAProceedings of the 2010 International Conference on Field Programmable Logic and Applications10.1109/FPL.2010.94(464-468)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.1109/FPL.2010.94
Sllame A(2004)A model for a reusable system-on-a-chip hardware component integrated with design exploration methodology4th IEEE International Workshop on System-on-Chip for Real-Time Applications10.1109/IWSOC.2004.1319895(287-290)Online publication date: 2004
https://doi.org/10.1109/IWSOC.2004.1319895

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Behavioral Synthesis and Component Reuse with VHDL

Integration of behavioral and layout synthesis: a chip synthesis approach

Optimizing equivalence checking for behavioral synthesis

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Behavioral Synthesis and Component Reuse with VHDL

Integration of behavioral and layout synthesis: a chip synthesis approach

Optimizing equivalence checking for behavioral synthesis

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