Article

Free access

Low-power design of sequential circuits using a quasi-synchronous derived clock

Authors:

Xunwei Wu,

Jian Wei,

Massoud Pedram,

Qing WuAuthors Info & Claims

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Pages 345 - 350

https://doi.org/10.1145/368434.368672

Published: 28 January 2000 Publication History

PDF eReader

References

[1]

J. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, Norwell, 1996.

Digital Library

Google Scholar

[2]

The National Technology Roadmap for Semiconductors, Technology needs, Semiconductor Industry Association, pp.17-18, the 1997 Edition.

Google Scholar

[3]

G. Friedman, "Clock distribution design in VLSI circuits: an overview," Proc. IEEE ISCAS, San Jose, pp. 1475-1478, 1994.

Google Scholar

[4]

R. Hossain, L. D. Wronski and A. Albicki, "Low power design using double edge triggered flip-flops," IEEE Trans. VLSI Systems, vol.2, no.2, pp. 261-265, June 1994.

Digital Library

Google Scholar

[5]

M. Pedram, Q. Wu and X. Wu, "A new design of double edge triggered flip-flops", Proc. ASP-DAC, Yokohama, pp. 417-421, Feb. 1998.

Crossref

Google Scholar

[6]

L. Benini and G. De Micheli, "Transformation and synthesis of FSMs for low power gated clock implementation", Proc. Int. Symp. Workshop on Low Power Design, pp.21-26, Apr. 1995.

Digital Library

Google Scholar

[7]

N. H. E. West, K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective,2 nd Edition, Addison-Wesley Publishing Co., New Work, 1993.

Digital Library

Google Scholar

Cited By

View all

C KV P KV R BC N M(2024)ENERGY EFFICIENT WALLACE MULTIPLIER USING SYMMETRIC STACKING COUNTER CIRCUITMeasurement: Sensors10.1016/j.measen.2024.101267(101267)Online publication date: Jun-2024
https://doi.org/10.1016/j.measen.2024.101267
Singh SGupta MChauhan R(2020)Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating TechniquesNanoelectronics, Circuits and Communication Systems10.1007/978-981-15-7486-3_27(277-288)Online publication date: 18-Nov-2020
https://doi.org/10.1007/978-981-15-7486-3_27
Gupta MSingh SChauhan R(2020)Design of High-Speed Binary Counter Architecture for Low-Power ApplicationsNanoelectronics, Circuits and Communication Systems10.1007/978-981-15-7486-3_13(119-129)Online publication date: 18-Nov-2020
https://doi.org/10.1007/978-981-15-7486-3_13
Show More Cited By

Low-power design of sequential circuits using a quasi-synchronous derived clock
1. Hardware

Recommendations

Accelerating Synchronous Sequential Circuits Using an Adaptive Clock
VLSID '10: Proceedings of the 2010 23rd International Conference on VLSI Design

In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a ...
Activity-driven clock design for low power circuits
ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree can be turned on/off by gating the clock signals during the active/idle ...
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95: Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and power dissipation, without changing logic functionality. In this paper, we ...

Comments

Information & Contributors

Information

Published In

ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference

January 2000

691 pages

ISBN:0780359747

DOI:10.1145/368434

Chairman:
Kenji Yoshida
Toshiba Corp., Kawasaki, Japan

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 January 2000

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASP-DAC00

Sponsor:

IEICE
IPSJ
SIGDA
IEEE-CAS

ASP-DAC00: Asia and South Pacific Design Automation Conference 2000

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
314
Total Downloads

Downloads (Last 12 months)15
Downloads (Last 6 weeks)3

Reflects downloads up to 04 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

C KV P KV R BC N M(2024)ENERGY EFFICIENT WALLACE MULTIPLIER USING SYMMETRIC STACKING COUNTER CIRCUITMeasurement: Sensors10.1016/j.measen.2024.101267(101267)Online publication date: Jun-2024
https://doi.org/10.1016/j.measen.2024.101267
Singh SGupta MChauhan R(2020)Design and FPGA Synthesis of an Efficient Synchronous Counter with Clock-Gating TechniquesNanoelectronics, Circuits and Communication Systems10.1007/978-981-15-7486-3_27(277-288)Online publication date: 18-Nov-2020
https://doi.org/10.1007/978-981-15-7486-3_27
Gupta MSingh SChauhan R(2020)Design of High-Speed Binary Counter Architecture for Low-Power ApplicationsNanoelectronics, Circuits and Communication Systems10.1007/978-981-15-7486-3_13(119-129)Online publication date: 18-Nov-2020
https://doi.org/10.1007/978-981-15-7486-3_13
Syuhadah Amran NHawa Ruslan S(2018)Low Power 130 nm CMOS Johnson Counter with Clock Gating TechniqueJournal of Physics: Conference Series10.1088/1742-6596/1049/1/0120731049(012073)Online publication date: 20-Jul-2018
https://doi.org/10.1088/1742-6596/1049/1/012073
Katreepalli RHaniotakis T(2017)Energy-efficient synchronous counter design with minimum hardware overhead2017 International Conference on Communication and Signal Processing (ICCSP)10.1109/ICCSP.2017.8286619(1423-1427)Online publication date: Apr-2017
https://doi.org/10.1109/ICCSP.2017.8286619
Guang-Ping Xiang Ji-Zhong Shen Xue-Xiang Wu Liang Geng (2013)Design of a low-power pulse-triggered flip-flop with conditional clock technique2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)10.1109/ISCAS.2013.6571797(121-124)Online publication date: May-2013
https://doi.org/10.1109/ISCAS.2013.6571797
Ismail SRahman AIslam F(2012)Low power design of Johnson Counter using clock gating2012 15th International Conference on Computer and Information Technology (ICCIT)10.1109/ICCITechn.2012.6509803(510-517)Online publication date: Dec-2012
https://doi.org/10.1109/ICCITechn.2012.6509803
Ismail SRahman SRahman MFerdous N(2012)A Design Scheme of Toggle Operation Based Johnson Counter with Efficient Clock GatingProceedings of the 2012 Fourth International Conference on Computational Intelligence, Modelling and Simulation10.1109/CIMSim.2012.52(393-399)Online publication date: 25-Sep-2012
https://dl.acm.org/doi/10.1109/CIMSim.2012.52
Pengjun Wang Ying Liu Dao Huang (2004)Energy-information-recovery low-power flip-flop based on three-phase-clock and its applicationProceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication (IEEE Cat. No.04EX710)10.1109/CASSET.2004.1322964(237-240)Online publication date: 2004
https://doi.org/10.1109/CASSET.2004.1322964
Wu XPedram M(2000)Low power sequential circuit design by using priority encoding and clock gatingProceedings of the 2000 international symposium on Low power electronics and design10.1145/344166.344557(143-148)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1145/344166.344557

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Recommendations

Accelerating Synchronous Sequential Circuits Using an Adaptive Clock

Activity-driven clock design for low power circuits

Optimization of combinational and sequential logic circuits for low power using precomputation

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Recommendations

Accelerating Synchronous Sequential Circuits Using an Adaptive Clock

Activity-driven clock design for low power circuits

Optimization of combinational and sequential logic circuits for low power using precomputation

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations