Article

Multi-GHz interconnect effects in microprocessors

Authors:

Phillip J. Restle,

Albert E. Ruehli,

Steven G. WalkerAuthors Info & Claims

ISPD '01: Proceedings of the 2001 international symposium on Physical design

Pages 93 - 97

https://doi.org/10.1145/369691.369743

Published: 01 April 2001 Publication History

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Abstract

High frequency on-chip interconnect examples are accurately analyzed using full-wave PEEC (Partial Element Equivalent Circuit) analysis. All wire currents and voltages (or delays) are visualized using 3D animations to aid intuitive understanding of new, high frequency interconnect effects.

References

[1]

A. Deutsch, G. V. Kopcsay, P. Restle, et al, "When are Transmission-Line Effects Important for On Chip Interconnections?" IEEE Trans. Microwave Theory Tech. (USA) Vol. 45, No. 10, pt. 2, pp. 1836-46, Oct. 1997.

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[2]

P. J. Restle, K. A. Jenkins, A. Deutsch and P. W. Cook, "Measurement and Modeling of On-Chip Transmission-Line Effects in a 400 MHz Microprocessor," IEEE Journal of Solid- State Circuits, Vol. 33 No. 4, pp. 662-665, Apr. 1998.

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[3]

P. J. Restle, A. E. Ruehli, S. G. Walker, "Dealing with Inductance in High-Speed Chip Design," In Proc. of the Design Automation Conf., pp 904-909, June 1999, New Orleans, LA.

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[4]

P. J. Restle, A. E. Ruehli, S. G. Walker, G. Papadopoulos, "Full-Wave PEEC Time-Domain Method for the Modeling of On-Chip Interconnects," IEEE Trans. on Computer-Aided Design, (in press).

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D. Dobberpuhl et al., "A 200 MHz 64-bit Dual Issue CMOS Microprocessor," IEEE J. Solid-State Circuits, Vol. 27, No. 11, 1992, pp. 1,555-1,567.

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S. Rusu, S. Tam, "Clock Generation and Distribution for a IA- 64 Microprocessor," IEEE ISSCC Tech. Dig. pp. 176-7, Feb. 2000.

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P. J. Restle et al, "A Clock Distribution Network for Microprocessors," Symposium on VLSI Circuits Digest of Technical Papers, June 2000, pp. 184-187, Honolulu, HI

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Cited By

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P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_8(129-144)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_8
Condley WHu XGuthaus MReda SWang J(2010)Analysis of high-performance clock networks with RLC and transmission line effectsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811113(51-58)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811113
Shelar R(2010)Routing with constraints for post-grid clock distribution in microprocessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.204001229:2(245-249)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2040012
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Published In

ISPD '01: Proceedings of the 2001 international symposium on Physical design

April 2001

245 pages

ISBN:1581133472

DOI:10.1145/369691

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 2001

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ISPD01: International Symposium on Physical Design

April 1 - 4, 2001

California, Sonoma, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

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P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Distribution NetworksOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_8(129-144)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_8
Condley WHu XGuthaus MReda SWang J(2010)Analysis of high-performance clock networks with RLC and transmission line effectsProceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction10.1145/1811100.1811113(51-58)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1811100.1811113
Shelar R(2010)Routing with constraints for post-grid clock distribution in microprocessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.204001229:2(245-249)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2040012
Shelar RNam GSaxena P(2009)An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessorsProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514964(141-148)Online publication date: 29-Mar-2009
https://dl.acm.org/doi/10.1145/1514932.1514964
Wilke GFonseca RMezzomo CReis RLubaszewski MRenovell MGupta R(2008)A novel scheme to reduce short-circuit power in mesh-based clock architecturesProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404409(117-122)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1145/1404371.1404409
Shelar RMadden PPan D(2007)An efficent clustering algorithm for low power clock tree synthesisProceedings of the 2007 international symposium on Physical design10.1145/1231996.1232037(181-188)Online publication date: 18-Mar-2007
https://dl.acm.org/doi/10.1145/1231996.1232037
Feng ZLi PHu J(2006)Efficient Model Update for General Link-Insertion NetworksProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.55(43-50)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.55
Lu BHu JEllis GSu HPedram MAlpert C(2003)Process variation aware clock tree routingProceedings of the 2003 international symposium on Physical design10.1145/640000.640037(174-181)Online publication date: 6-Apr-2003
https://dl.acm.org/doi/10.1145/640000.640037
Su HSapatnekar SErnst R(2001)Hybrid structured clock network constructionProceedings of the 2001 IEEE/ACM international conference on Computer-aided design10.5555/603095.603163(333-336)Online publication date: 4-Nov-2001
https://dl.acm.org/doi/10.5555/603095.603163
Haihua Su Sapatnekar S(2001)Hybrid structured clock network constructionIEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)10.1109/ICCAD.2001.968643(333-336)Online publication date: 2001
https://doi.org/10.1109/ICCAD.2001.968643

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