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Dynamic management of scratch-pad memory space

Published: 22 June 2001 Publication History
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  • Abstract

    Optimizations aimed at improving the efficiency of on-chip memories are extremely important. We propose a compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework that uses both loop and data transformations. Experimental results obtained using a generic cost model indicate significant reductions in data transfer activity between SPM and off-chip memory.

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    • (2024)Memory-processor co-scheduling of AECR-DAG real-time tasks on partitioned multicore platforms with scratchpadsJournal of Systems Architecture10.1016/j.sysarc.2024.103117150(103117)Online publication date: May-2024
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    cover image ACM Conferences
    DAC '01: Proceedings of the 38th annual Design Automation Conference
    June 2001
    863 pages
    ISBN:1581132972
    DOI:10.1145/378239
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 22 June 2001

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    • (2024)Compiler-Based Memory Encryption for Machine Learning on Commodity Low-Power DevicesProceedings of the 33rd ACM SIGPLAN International Conference on Compiler Construction10.1145/3640537.3641564(198-211)Online publication date: 17-Feb-2024
    • (2024)Memory-processor co-scheduling of AECR-DAG real-time tasks on partitioned multicore platforms with scratchpadsJournal of Systems Architecture10.1016/j.sysarc.2024.103117150(103117)Online publication date: May-2024
    • (2020)Methodology for the Placement of Dynamic Data ObjectsHeterogeneous Memory Organizations in Embedded Systems10.1007/978-3-030-37432-7_4(53-98)Online publication date: 31-Jan-2020
    • (2020)Related WorkHeterogeneous Memory Organizations in Embedded Systems10.1007/978-3-030-37432-7_2(23-33)Online publication date: 31-Jan-2020
    • (2020)Space‐address decoupled scratchpad memory management for neural network acceleratorsConcurrency and Computation: Practice and Experience10.1002/cpe.604633:6Online publication date: 13-Oct-2020
    • (2019)Developments in memory management in OpenMPInternational Journal of High Performance Computing and Networking10.5555/3302714.330271913:1(70-85)Online publication date: 1-Jan-2019
    • (2019)Optimizing tensor contractions for embedded devices with racetrack memory scratch-padsProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326351(5-18)Online publication date: 23-Jun-2019
    • (2019)SA-SPM: an efficient compiler for security aware scratchpad memory (invited paper)Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326347(57-69)Online publication date: 23-Jun-2019
    • (2018)ShaVe-ICEACM Transactions on Embedded Computing Systems10.1145/315766717:2(1-25)Online publication date: 5-Feb-2018
    • (2018)A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad MemoryIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.278522226:4(663-670)Online publication date: Apr-2018
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