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Instruction flow-based front-end throttling for power-aware high-performance processors

Authors:

Amirali Baniasadi,

Andreas MoshovosAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 16 - 21

https://doi.org/10.1145/383082.383088

Published: 06 August 2001 Publication History

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References

[1]

T. Burd and B. Peters. A Power Analysis of a Microprocessor: A Study of the MIPS R3000 Architecture. ERL Technical Report, University of California, Berkeley, May 1994.

Google Scholar

[2]

E. Jacobsen, E. Rotenberg, and J. E. Smith. Assigning Confidence to Conditional Branch Predictions. In Proc. Intl. Symposium on Microarchitecture, December 1996.

Digital Library

Google Scholar

[3]

S. Manne, A. Klauser and D. Grunwald. Pipeline Gating: Speculation Control For Energy Reduction. In Proc. Intl. Symposium on Computer Architecture, Jun, 1998.

Digital Library

Google Scholar

[4]

D. Grunwald, A. Klusser, S. Manne and A. Plezkun, Confidence Estimation for Speculation Control, In Proc. Intl. Symposium on Computer Architecture, Jun, 1998.

Digital Library

Google Scholar

[5]

H. Sanchez et al. Thermal management systems for high performance PowerPC microprocessors. In Proc. COMPCON '97, February, 1997.

Digital Library

Google Scholar

Cited By

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Zhang WZhang HLach J(2021)Extending Performance-Energy Trade-offs Via Dynamic Core ScalingIEEE Transactions on Computers10.1109/TC.2020.302930670:11(1875-1886)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TC.2020.3029306
Sarangi SGoel SSingh BHaddad HWainwright RChbeir R(2018)Energy efficient scheduling in IoT networksProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167213(733-740)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167213
Khavari Tavana MHajkazemi MPathak DSavidis IHomayoun H(2018)ElasticCoreIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275921926:2(249-261)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2759219
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Index Terms

Instruction flow-based front-end throttling for power-aware high-performance processors
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Electronic design automation
    1. Modeling and parameter extraction
  2. Hardware validation

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01

Sponsor:

SIGDA

ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

Acceptance Rates

ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Zhang WZhang HLach J(2021)Extending Performance-Energy Trade-offs Via Dynamic Core ScalingIEEE Transactions on Computers10.1109/TC.2020.302930670:11(1875-1886)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TC.2020.3029306
Sarangi SGoel SSingh BHaddad HWainwright RChbeir R(2018)Energy efficient scheduling in IoT networksProceedings of the 33rd Annual ACM Symposium on Applied Computing10.1145/3167132.3167213(733-740)Online publication date: 9-Apr-2018
https://dl.acm.org/doi/10.1145/3167132.3167213
Khavari Tavana MHajkazemi MPathak DSavidis IHomayoun H(2018)ElasticCoreIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275921926:2(249-261)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2759219
(2017)Evaluating impact on CMPs' power for design inaccuracy diagnosisInternational Journal of Computer Applications in Technology10.1504/IJCAT.2017.08819556:3(198-209)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1504/IJCAT.2017.088195
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_28-2(1-46)Online publication date: 11-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_28-2
Park YKhajeh AShin JKurdahi FEltawil ADutt N(2017)Microarchitecture-Level SoC DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_28(867-913)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_28
Chen YCong JGill MReinman GXiao B(2015)Customizable ComputingSynthesis Lectures on Computer Architecture10.2200/S00650ED1V01Y201505CAC03310:3(1-118)Online publication date: 6-Jul-2015
https://doi.org/10.2200/S00650ED1V01Y201505CAC033
Jundt ACauble-Chantrenne ATiwari APeraza JLaurenzano MCarrington LCameron KHoisie AKerbyson DLowenthal DNikolopoulos DYalamanchili SCarrington LManzano J(2015)Compute bottlenecks on the new 64-bit ARMProceedings of the 3rd International Workshop on Energy Efficient Supercomputing10.1145/2834800.2834806(1-7)Online publication date: 15-Nov-2015
https://dl.acm.org/doi/10.1145/2834800.2834806
Tavana MHajkazemi MPathak DSavidis IHomayoun H(2015)ElasticCoreProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744833(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744833
Zhang WZhang HLach J(2015)Dynamic core scalingProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357120(319-326)Online publication date: 18-Oct-2015
https://dl.acm.org/doi/10.1109/ICCD.2015.7357120
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A low power front-end for embedded processors using a block-aware instruction set

Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures