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Measurement and evaluation of the MIPS architecture and processor

Editor: Anita K. Jones Authors:

Thomas R. Gross,

John L. Hennessy,

Steven A. Przybylski,

Christopher RowenAuthors Info & Claims

ACM Transactions on Computer Systems (TOCS), Volume 6, Issue 3

Pages 229 - 257

https://doi.org/10.1145/45059.45060

Published: 01 August 1988 Publication History

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Abstract

MIPS is a 32-bit processor architecture that has been implemented as an nMOS VLSI chip. The instruction set architecture is RISC-based. Close coupling with compilers and efficient use of the instruction set by compiled programs were goals of the architecture. The MIPS architecture requires that the software implement some constraints in the design that are normally considered part of the hardware implementation. This paper presents experimental results on the effectiveness of this processor as a program host. Using sets of large and small benchmarks, the instruction and operand usage patterns are examined both for optimized and unoptimized code. Several of the architectural and organizational innovations in MIPS, including software pipeline scheduling, multiple-operation instructions, and word-based addressing, are examined in light of this data.

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Cited By

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Al-Qasmi AAl Shuaily HEhimwenma KAl Sharji S(2023)Scalability of IoT Systems: Do Execution Costs Predict the Quality of Service?Internet of Everything10.1007/978-3-031-25222-8_8(91-100)Online publication date: 29-Jan-2023
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Richardson WBrunvand E(1996)FredProceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems10.5555/785164.785210Online publication date: 18-Mar-1996
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Index Terms

Measurement and evaluation of the MIPS architecture and processor

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Reviews

Reviewer: Lanfranco Lopriore

This paper presents the results of a large number of measurements on the performance of MIPS, a 32-bit reduced instruction set computer (RISC) architecture implemented at Stanford University between 1981 and 1984 as a single-chip microprocessor. Special features of this architecture are word addressing, multiple-operation instructions, and pipelining. The measurements were performed by executing a set of benchmark programs, written in Pascal and C, whose lengths ranged from 32 to 14,311 lines of source code (the static and dynamic characteristics of each program are carefully reported). The paper pays special attention not only to the salient features of the instruction set performance (e.g., operation code distribution and addressing mode utilization), but also to such important aspects of the internal organization of the architecture as the use of machine resources and the efficiency of the pipeline. An attempt is made to compare some of these results with data available in the literature for the VAX architecture. Unfortunately, this issue is addressed only marginally. The paper gives a brief but adequate description of the MIPS architecture. The references include introductory works on the RISC concept as well as several papers, written by the members of the MIPS project team, in which the reader can find the rationale for the MIPS design. An in-depth examination of the architectural implications of each measurement is also provided. As the authors carefully point out, measurements depend on the benchmark programs as well as on the machine-compiler complex. In spite of this fact, this self-contained and well-structured paper is definitely useful reading for every computer architect involved in instruction set design.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1988

Published in TOCS Volume 6, Issue 3

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Al-Qasmi AAl Shuaily HEhimwenma KAl Sharji S(2023)Scalability of IoT Systems: Do Execution Costs Predict the Quality of Service?Internet of Everything10.1007/978-3-031-25222-8_8(91-100)Online publication date: 29-Jan-2023
https://doi.org/10.1007/978-3-031-25222-8_8
Chang PMahlke SChen WHwu W(2006)Profile‐guided automatic inline expansion for C programsSoftware: Practice and Experience10.1002/spe.438022050222:5(349-369)Online publication date: 30-Oct-2006
https://doi.org/10.1002/spe.4380220502
Richardson WBrunvand E(1996)FredProceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems10.5555/785164.785210Online publication date: 18-Mar-1996
https://dl.acm.org/doi/10.5555/785164.785210
Richardson WBrunvand E(1996)Fred: an architecture for a self-timed decoupled computerProceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems10.1109/ASYNC.1996.494438(60-68)Online publication date: 1996
https://doi.org/10.1109/ASYNC.1996.494438
Abnous ABagherzadeh N(1994)Pipelining and Bypassing in a VLIW ProcessorIEEE Transactions on Parallel and Distributed Systems10.1109/71.2856125:6(658-664)Online publication date: 1-Jun-1994
https://dl.acm.org/doi/10.1109/71.285612
Esponda MRojas R(1992)A graphical comparison of RISC processorsACM SIGARCH Computer Architecture News10.1145/142880.14288420:4(2-8)Online publication date: 1-Sep-1992
https://dl.acm.org/doi/10.1145/142880.142884
Koldinger EEggers SLevy H(1991)On the validity of trace-driven simulation for multiprocessorsACM SIGARCH Computer Architecture News10.1145/115953.11597719:3(244-253)Online publication date: 1-Apr-1991
https://dl.acm.org/doi/10.1145/115953.115977
Vajapeyam SSohi GHsu W(1991)An empirical study of the CRAY Y-MP processor using the Perfect club benchmarksACM SIGARCH Computer Architecture News10.1145/115953.11597019:3(170-179)Online publication date: 1-Apr-1991
https://dl.acm.org/doi/10.1145/115953.115970
Koldinger EEggers SLevy HVranesic Z(1991)On the validity of trace-driven simulation for multiprocessorsProceedings of the 18th annual international symposium on Computer architecture10.1145/115952.115977(244-253)Online publication date: 1-Apr-1991
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Vajapeyam SSohi GHsu WVranesic Z(1991)An empirical study of the CRAY Y-MP processor using the Perfect club benchmarksProceedings of the 18th annual international symposium on Computer architecture10.1145/115952.115970(170-179)Online publication date: 1-Apr-1991
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A design of EPIC type processor based on MIPS architecture

MIPS: a VLSI processor architecture

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