Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/503048.503081acmconferencesArticle/Chapter ViewAbstractPublication PagesfpgaConference Proceedingsconference-collections
Article

A dynamically reconfigurable adaptive viterbi decoder

Published: 24 February 2002 Publication History

Abstract

The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital communication channels. Although widely-used, the most popular communications decoding algorithm, the Viterbi algorithm, requires an exponential increase in hardware complexity to achieve greater decode accuracy. In this paper, we describe the analysis and implementation of a reduced-complexity decode approach, the adaptive Viterbi algorithm (AVA). Our AVA design is implemented in reconfigurable hardware to take full advantage of algorithm parallelism and specialization. Run-time dynamic reconfiguration is used in response to changing channel noise conditions to achieve improved decoder performance. Implementation parameters for the decoder have been determined through simulation and the decoder has been implemented on a Xilinx XC4036-based PCI board. An overall decode performance improvement of 7.5X for AVA has been achieved versus algorithm implementation on a Celeron-processor based system. The use of dynamic reconfiguration leads to a 20% performance improvement over a static implementation with no loss of decode accuracy.

References

[1]
Altera Corporation.Apex II data sheet,2001. http://www.altera.com.
[2]
Annapolis Microsystems,Inc.WILD-ONE Reference Manual,1999.
[3]
W.Burleson,R.Tessier,D.Goeckel,S.Swaminathan, P Jain,J.Euh,S.Venkatraman,and V.Thyagarajan. Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations for Improved Performance and Reduced Power.In IEEE Conference on Acoustics,Speech,and Signal Processing,May 2001.
[4]
F.Chan and D.Haccoun.Adaptive Viterbi Decoding of Convolutional Codes over Memoryless Channels. IEEE Transactions on Communications, 45(11):1389 -1400,Nov.1997.
[5]
M.Kivioja,J.Isoaho,and L.Vanska.Design and Implementation of a Viterbi Decoder with FPGAs. Journal of VLSI Signal Processing,21(1):5 -14,May 1999.
[6]
C.F.Lin and J.B.Anderson.M-algorithm Decoding of Channel Convolutional Codes.In Proceedings, Princeton Conference of Information Science and Systems,pages 362 -366,Princeton,NJ,Mar.1986.
[7]
A.Michelson and A.Levesque.Error-control Techniques for Digital Communication John Wiley and Sons,New York,NY,1985.
[8]
B.Pandita and S.K.Roy Design and Implementation of a Viterbi Decoder Using FPGAs.In Proceedings, IEEE International Conference on VLSI Design, pages 611 -614,Jan.1999.
[9]
J.Proakis.Digital Communications McGraw-Hill, New York,NY,1995.
[10]
H.Schmit and D.Thomas.Hidden Markov Modelling and Fuzzy Controllers in FPGAs.In Proceedings, IEEE Workshop on FPGA-base Custom Computing Machines,pages 214 -221,Napa,Ca,Apr.1995.
[11]
S.J.Simmons.Breath-.rst Trellis Decoding with Adaptive E .ort.IEEE Transactions on Communications,38:3 -12,Jan.1990.
[12]
S.Swaminathan.An FPGA-based Adaptive Viterbi Decoder.Master 's thesis,University of Massachusetts, Amherst,Department of Electrical and Computer Engineering,2001.
[13]
R.Tessier and W.Burleson.Recon .gurable Computing and Digital Signal Processing:A Survey. Journal of VLSI Signal Processing,28(1):7 -27,May 2001.
[14]
Texas Instruments,Inc.TMS320C6201 DSP Data Sheet,2001.
[15]
Xilinx Corporation.Virtex II data sheet,2001. http://www.xilinx.com.
[16]
D.Yeh,G.Feygin,and P Chow.RACER:A Recon .gurable Constraint-Length 14 Viterbi Decoder. In Proceedings,IEEE Workshop on FPGA-base Custom Computing Machines,Napa,Ca,Apr.1996.

Cited By

View all
  • (2024)On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)ACM Transactions on Reconfigurable Technology and Systems10.1145/363320417:2(1-28)Online publication date: 30-Apr-2024
  • (2021)Low Complexity Modified Viterbi Decoder with Convolution Codes for Power Efficient Wireless CommunicationWireless Personal Communications10.1007/s11277-021-08919-w122:1(685-700)Online publication date: 27-Aug-2021
  • (2018)180 Mbps Viterbi Decoder Design on FPGA for OFDM Modulator in Underwater Communication ApplicationsInternational Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 201810.1007/978-3-030-03146-6_35(319-326)Online publication date: 21-Dec-2018
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
February 2002
257 pages
ISBN:1581134525
DOI:10.1145/503048
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2002

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. FPGA
  2. Viterbi coding
  3. dynamic reconfiguration

Qualifiers

  • Article

Conference

FPGA02
Sponsor:

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)7
  • Downloads (Last 6 weeks)3
Reflects downloads up to 02 Sep 2024

Other Metrics

Citations

Cited By

View all
  • (2024)On the Malicious Potential of Xilinx’s Internal Configuration Access Port (ICAP)ACM Transactions on Reconfigurable Technology and Systems10.1145/363320417:2(1-28)Online publication date: 30-Apr-2024
  • (2021)Low Complexity Modified Viterbi Decoder with Convolution Codes for Power Efficient Wireless CommunicationWireless Personal Communications10.1007/s11277-021-08919-w122:1(685-700)Online publication date: 27-Aug-2021
  • (2018)180 Mbps Viterbi Decoder Design on FPGA for OFDM Modulator in Underwater Communication ApplicationsInternational Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 201810.1007/978-3-030-03146-6_35(319-326)Online publication date: 21-Dec-2018
  • (2017)STA compatible backend design flow for TSV-based 3-D ICs2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918314(186-190)Online publication date: Mar-2017
  • (2017)Voltage scaling for 3-D ICsMicroelectronics Journal10.1016/j.mejo.2017.09.00569:C(35-44)Online publication date: 1-Nov-2017
  • (2016)Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal AssistantACM Transactions on Computer Systems10.1145/287063134:1(1-32)Online publication date: 6-Apr-2016
  • (2015)SiriusACM SIGARCH Computer Architecture News10.1145/2786763.269434743:1(223-238)Online publication date: 14-Mar-2015
  • (2015)SiriusACM SIGPLAN Notices10.1145/2775054.269434750:4(223-238)Online publication date: 14-Mar-2015
  • (2015)SiriusProceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/2694344.2694347(223-238)Online publication date: 14-Mar-2015
  • (2015)Reconfigurable Computing ArchitecturesProceedings of the IEEE10.1109/JPROC.2014.2386883103:3(332-354)Online publication date: Mar-2015
  • Show More Cited By

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media