Article

Reconfigurable repetitive padding unit

Authors:

Georgi Kuzmanov,

Stamatis VassiliadisAuthors Info & Claims

GLSVLSI '02: Proceedings of the 12th ACM Great Lakes symposium on VLSI

Pages 98 - 103

https://doi.org/10.1145/505306.505328

Published: 18 April 2002 Publication History

Abstract

This paper proposes a reconfigurable processing unit, which performs the MPEG-4 repetitive padding algorithm in real time. The padding unit has been implemented as a scalable systolic structure of processing elements. A generic array of PE has been described in VHDL, and the functionality of the unit has been validated by simulations. In order to determine the chip area and speed of the padding structure, we have synthesized the structure for two FPGA families - Xilinx and Altera. The simulation results indicate that the proposed padding unit can operate in a wide frequency range, depending on the implemented configuration. It is shown that it can process from tens up to hundreds of thousands MPEG-4 macroblocks per second. This allows the real-time requirements of all MPEG-4 profiles and levels to be met efficiently at trivial hardware costs. Finally, the trade-off between chip-area and operating speed is discussed and possible configuration alternatives are proposed.

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Cited By

Wong SStougie BCotofana S(2002)Alternatives in FPGA-based SAD implementations2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.10.1109/FPT.2002.1188733(449-452)Online publication date: 2002
https://doi.org/10.1109/FPT.2002.1188733

Index Terms

Reconfigurable repetitive padding unit
1. Hardware

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Published In

cover image ACM Conferences

GLSVLSI '02: Proceedings of the 12th ACM Great Lakes symposium on VLSI

April 2002

194 pages

ISBN:1581134622

DOI:10.1145/505306

General Chairs:
Kanad Ghose
State Univ. of New York, Binghamton
,
Patrick H. Madden
State Univ. of New York, Binghamton
,
Program Chairs:
Vivek De
Intel
,
Peter M. Kogge
Univ. of Notre Dame

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 April 2002

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GLSVLSI02: Great Lakes Symposium on VLSI

April 18 - 19, 2002

New York, New York, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Wong SStougie BCotofana S(2002)Alternatives in FPGA-based SAD implementations2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.10.1109/FPT.2002.1188733(449-452)Online publication date: 2002
https://doi.org/10.1109/FPT.2002.1188733

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