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An effective congestion driven placement framework

Published: 07 April 2002 Publication History

Abstract

We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

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Cited By

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  • (2022)Pin density technique for congestion estimation and reduction of optimized design during placement and routingApplied Nanoscience10.1007/s13204-021-02173-z13:3(1819-1828)Online publication date: 30-Jan-2022
  • (2019)Routability-driven Placement for Mixed-size Designs using Design-hierarchy and Pin Information2019 International Conference on Automation, Computational and Technology Management (ICACTM)10.1109/ICACTM.2019.8776791(424-430)Online publication date: Apr-2019
  • (2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
  • Show More Cited By

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cover image ACM Conferences
ISPD '02: Proceedings of the 2002 international symposium on Physical design
April 2002
216 pages
ISBN:1581134606
DOI:10.1145/505388
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 April 2002

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ISPD02: International Symposium on Physical Design
April 7 - 10, 2002
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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

View all
  • (2022)Pin density technique for congestion estimation and reduction of optimized design during placement and routingApplied Nanoscience10.1007/s13204-021-02173-z13:3(1819-1828)Online publication date: 30-Jan-2022
  • (2019)Routability-driven Placement for Mixed-size Designs using Design-hierarchy and Pin Information2019 International Conference on Automation, Computational and Technology Management (ICACTM)10.1109/ICACTM.2019.8776791(424-430)Online publication date: Apr-2019
  • (2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
  • (2017)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036681(15-21)Online publication date: 19-Mar-2017
  • (2017)Optimization of wire-length and block rearrangements for a modern IC placement using evolutionary techniques2017 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS)10.1109/ITCOSP.2017.8303081(1-4)Online publication date: Mar-2017
  • (2016)Placement: From Wirelength to Detailed RoutabilityIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.9.29(2-12)Online publication date: 2016
  • (2016)Digital Layout: PlacementElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-7(109-132)Online publication date: 14-Apr-2016
  • (2016)BEOL stack-aware routability prediction from placement using data mining techniques2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753259(41-48)Online publication date: Oct-2016
  • (2015)Progress and Challenges in VLSI Placement ResearchProceedings of the IEEE10.1109/JPROC.2015.2478963103:11(1985-2003)Online publication date: Nov-2015
  • (2014)Fast and Effective Congestion Refinement TechniqueApplied Mechanics and Materials10.4028/www.scientific.net/AMM.530-531.936530-531(936-942)Online publication date: Feb-2014
  • Show More Cited By

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