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Tera hardware-software cooperation

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Richard KorryAuthors Info & Claims

SC '97: Proceedings of the 1997 ACM/IEEE conference on Supercomputing

Pages 1 - 16

https://doi.org/10.1145/509593.509631

Published: 15 November 1997 Publication History

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Abstract

The development of Tera's MTA system was unusual. It respected the need for fast hardware and large shared memory, facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean machine model enabling calculated compiler optimizations and easy programming; and the need for novel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that offers high performance and ease of programming by virtue not only of fast physical hardware and flat shared memory, but also of the streamlined software systems that well utilize the features of the architecture intended to support them.

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Tera hardware-software cooperation
1. Theory of computation
  1. Models of computation
    1. Concurrency

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SC '97: Proceedings of the 1997 ACM/IEEE conference on Supercomputing

November 1997

921 pages

ISBN:0897919858

DOI:10.1145/509593

General Chair:
Dona Crawford

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 15 November 1997

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SC '97: International Conference for High Performance Computing, Networking, Storage and Analysis

November 15 - 21, 1997

CA, San Jose

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Multi-processor performance on the Tera MTA

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Multi-processor performance on the Tera MTA

An initial evaluation of the Tera Multithreaded Architecture and programming system using the C3I parallel benchmark suite

Performance analysis and portability issues of 64-bit message passing interface for Tera scale system

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