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High-Level specification and automatic generation of IP interface monitors

Published: 10 June 2002 Publication History

Abstract

A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attack this problem, several researchers have proposed monitor-based methodologies, which offer many benefits. This paper presents a novel, high-level specification style for these monitors, along with a linear-size, linear-time translation algorithm into monitor circuits. The specification style naturally fits the complex, but well-specified interfaces used between IP blocks in systems-on-chip. To demonstrate the advantage of our specification style, we have specified monitors for various versions of the Sonics OCP protocol as well as the AMBA AHB protocol, and have developed a prototype tool that automatically translates specifications into Verilog or VHDL monitor circuits.

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  • (2008)Augmenting a regular expression-based temporal logic with local variablesProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517447(1-8)Online publication date: 17-Nov-2008
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cover image ACM Conferences
DAC '02: Proceedings of the 39th annual Design Automation Conference
June 2002
956 pages
ISBN:1581134614
DOI:10.1145/513918
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 June 2002

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Author Tags

  1. alternation
  2. formal verification
  3. pipelining
  4. regular expressions

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DAC02: 39th Design Automation Conference
June 10 - 14, 2002
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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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  • (2013)Generating concise assertions with complete coverageProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483088(185-190)Online publication date: 2-May-2013
  • (2010)HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification MechanismsIEICE Transactions on Information and Systems10.1587/transinf.E93.D.2100E93-D:8(2100-2108)Online publication date: 2010
  • (2008)Augmenting a regular expression-based temporal logic with local variablesProceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design10.5555/1517424.1517447(1-8)Online publication date: 17-Nov-2008
  • (2007)Reactivity in systemC transaction-level modelsProceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing10.5555/1787497.1787507(34-50)Online publication date: 23-Oct-2007
  • (2007)Simulation vs. formalProceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing10.5555/1787497.1787499(1-7)Online publication date: 23-Oct-2007
  • (2007)Synthesizing SVA local variables for formal verificationProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278500(75-80)Online publication date: 4-Jun-2007
  • (2006)Toward diagrammability and efficiency in event-sequence languagesInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/2990015.32209358:4-5(431-447)Online publication date: 1-Aug-2006
  • (2006)Functional verification methodology based on formal interface specification and transactor generationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131762(1013-1018)Online publication date: 6-Mar-2006
  • (2006)Communication and co-simulation infrastructure for heterogeneous system integrationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131606(462-467)Online publication date: 6-Mar-2006
  • (2006)Extensible control architecturesProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176800(323-333)Online publication date: 22-Oct-2006
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