RISCY patents
Pages 169 - 191
References
[1]
[1] D.A. Patterson and D.R. Ditzel, "The Case for the Reduced Instruction Set Computer," Computer Architecture News, pp. 25-33, vol. 8, No. 6, 15 October 1980.
[2]
[2] D.W. Clark and W.D. Strecker, "Comments on 'The Case for the Reduced Instruction Set Computer'," Computer Architecture News, pp. 34-38, vol. 8, No. 6,15 October 1980.
[3]
[3] D.A. Patterson and C.H. Sequin, "RISC I: A Reduced Instruction Set VLSI Computer," Proc. 8th International Symposium on Computer Architecture, pp. 443-457, May 12-14, 1981, Minneapolis, Minnesota.
[4]
[4] D.T. Fitzpatrick et al., "VLSI Implementations of a Reduced Instruction Set Computer," Proceedings of the CMU Conference on VLSI Systems and Computations, October 19-21, 1981, Pittsburgh Pennsylvania.
[5]
[5] J.L. Hennessy et al., "MIPS: A VLSI Processor Architecture," Proc. CMU Conference on VLSI Systems and Computations, pages 337-346. Computer Science Press, October, 1981.
[6]
[6] J.L. Hennessy and T.R. Gross, "Code Generation and Reorganization in the Presence of Pipeline Constraints," Proc. Ninth POPL Conference, pages 120- 127. ACM, January, 1982.
[7]
[7] M.G.H. Katevenis et al.,"Datapath Design for RISC," Proc. Conference on Advanced Research in VLSI, Cambridge, Massachusetts, January 25-27, 1982.
[8]
[8] J.L. Hennessy et al., "The MIPS Machine," Proc. 20th Annual IEEE Computer Conference (COMPCON '82), February 24-26, 1982, San Francisco.
[9]
[9] D.A. Patterson, "A RISCy Approach to Microprocessor Technology," Proc. 20th Annual IEEE Computer Conference (COMPCON '82), February 24-26, 1982, San Francisco.
[10]
[10] J.L. Hennessy et al., "Hardware/Software Tradeoffs for Increased Performance," Proc. SIGARCH/SIGPLAN Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 2-11. ACM, Palo Alto, March, 1982.
[11]
[11] G. Radin, "The 801 Minicomputer," Proc. SIGARCH/SIGPLAN Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 39-47. ACM, Palo Alto, March, 1982.
[12]
[12] D.A. Patterson and R.S. Piepho, "RISC Assessment: A High-Level Language Experiment," 9th Annual Symposium on Computer Architecture, Austin, Texas, April 26-29, 1982. pp. 1-6.
[13]
[13] M. Auslander and M. Hopkins, "An Overview of the PL.8 Compiler," Proc. SIGPLAN Symp. on Compiler Construction, pp. 2-31, June 1982.
[14]
[14] D.A. Patterson and C.H. Sequin, "A VLSI RISC," Computer, vol. 15, No. 9, September, 1982.
[15]
[15] D.A. Patterson, J.K. Foderaro and K.S. Van Dyke, "Running RISC's," VLSI Design, vol. III, No. 5, September/October, 1982.
[16]
[16] J.L. Hennessy et al., "MIPS: A Microprocessor Architecture," Proc. Micro-15, pp. 17-22. IEEE, October, 1982.
[17]
[17] T.R. Gross and J.L. Hennessy, "Optimizing Delayed Branches," Proc. Micro-15, pp. 114-120. IEEE, October, 1982.
[18]
[18] J.L. Hennessy et al., "Design of a High Performance VLSI Processor," Proc. Third Caltech Conf. on VLSI, California Institute of Technology, Pasadena, Ca., March, 1983.
[19]
[19] D.A. Patterson, Editor. "CS 292R Final Reports," June 8, 1980. Contains ten papers.
[20]
[20] V. Markstein, J, Cocke, and P. Markstein, "Optimization of Range Checking," IBM Research Report RC8456, September 9, 1980.
[21]
[21] G.J. Chaitin et al., "Register Allocation by Coloring," IBM Research Report RC8395, 1981.
[22]
[22] G.J. Chaitin, "Register Allocation and Spilling via Coloring," IBM Research Report RC9124, 1981.
[23]
[23] D.A. Patterson, Editor. "Proceedings of CS 292R: Smalltalk On A RISC, Architectural Investigations," April 1983. Contains 12 papers.
[24]
[24] M.G.H. Katevenis, "Reduced Instruction Set Computer Architectures for VLSI," Report No. UCB/CSD 83/141, Computer Science Division (EECS), University of California, Berkeley, October, 1983.
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Published: 01 September 1988
Published in SIGARCH Volume 16, Issue 4
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