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Hierarchical registers for scientific computers

Authors:

J. A. Swensen,

Y. N. PattAuthors Info & Claims

ICS '88: Proceedings of the 2nd international conference on Supercomputing

Pages 346 - 354

https://doi.org/10.1145/55364.55398

Published: 01 June 1988 Publication History

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Abstract

Simulations of scientific programs running on traditional scientific computer architectures show that execution with hundreds of registers can be more than twice as fast as execution with only eight registers. In addition, execution with a small number of fast registers and hundreds of slower registers can be as fast as execution with hundreds of fast registers. A hierarchical organization of fast and slow registers is presented, register-allocation strategies are discussed, and a novel, indirect, register-addressing mechanism is described.

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Gudaparthi SShrestha R(2022)Selective register-file cache: an energy saving technique for embedded processor architectureDesign Automation for Embedded Systems10.1007/s10617-022-09264-226:2(105-124)Online publication date: 29-May-2022
https://doi.org/10.1007/s10617-022-09264-2
Sadrosadati MMirhosseini AHajiabadi AEhsani SFalahati HSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2021)Highly Concurrent Latency-tolerant Register Files for GPUsACM Transactions on Computer Systems10.1145/341997337:1-4(1-36)Online publication date: 4-Jan-2021
https://dl.acm.org/doi/10.1145/3419973
Esfeden HAbdolrashidi ARahman SWong DAbu-Ghazaleh N(2020)BOW: Breathing Operand Windows to Exploit Bypassing in GPUs2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00084(996-1008)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00084
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Hierarchical registers for scientific computers

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ICS '88: Proceedings of the 2nd international conference on Supercomputing

June 1988

679 pages

ISBN:0897912721

DOI:10.1145/55364

Editor:
J. Lenfant
Rennes

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1988

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Gudaparthi SShrestha R(2022)Selective register-file cache: an energy saving technique for embedded processor architectureDesign Automation for Embedded Systems10.1007/s10617-022-09264-226:2(105-124)Online publication date: 29-May-2022
https://doi.org/10.1007/s10617-022-09264-2
Sadrosadati MMirhosseini AHajiabadi AEhsani SFalahati HSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2021)Highly Concurrent Latency-tolerant Register Files for GPUsACM Transactions on Computer Systems10.1145/341997337:1-4(1-36)Online publication date: 4-Jan-2021
https://dl.acm.org/doi/10.1145/3419973
Esfeden HAbdolrashidi ARahman SWong DAbu-Ghazaleh N(2020)BOW: Breathing Operand Windows to Exploit Bypassing in GPUs2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00084(996-1008)Online publication date: Oct-2020
https://doi.org/10.1109/MICRO50266.2020.00084
Sadrosadati MMirhosseini AEhsani SSarbazi-Azad HDrumond MFalsafi BAusavarungnirun RMutlu O(2018)LTRFACM SIGPLAN Notices10.1145/3296957.317321153:2(489-502)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173211
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Mittal S(2016)A survey of techniques for designing and managing CPU register fileConcurrency and Computation: Practice and Experience10.1002/cpe.390629:4Online publication date: 13-Jul-2016
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Exploiting virtual registers to reduce pressure on real registers

Allocating architected registers through differential encoding

Doubling the number of registers on ARM processors

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Exploiting virtual registers to reduce pressure on real registers

Allocating architected registers through differential encoding

Doubling the number of registers on ARM processors

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