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Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew

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TAU '02: Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Pages 111 - 118

https://doi.org/10.1145/589411.589437

Published: 02 December 2002 Publication History

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Abstract

This paper describes a linear programming (LP) formulation for performance optimization of large-scale, synchronous circuits with level-sensitive latches. The proposed formulation permits circuits to operate at a higher clock frequency---that is, with a lower clock period---by the application of both non-zero clock skew scheduling [7] and time borrowing [9]. This LP formulation is computationally efficient and demonstrates significant circuit performance improvement. Unlike the approach documented in [2], the LP model of the clock period minimization problem presented here is stand-alone and independent of the specific LP solver (solution algorithm) used. The modified big M (MBM) method is introduced and applied to the linearization of the non-linear timing constraints of level-sensitive circuits into a solvable set of fully linear constraints. Clock period improvements as large as 63% are demonstrated over conventional flip-flop based circuits with zero clock skew. These improvements are shown on the ISCAS'89 benchmark circuits by using the industrial linear solver CPLEX [1].

References

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Cited By

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Broomhead DFurber SJohnson M(2013)Algebraic approach to time borrowingIET Computers & Digital Techniques10.1049/iet-cdt.2012.01037:1(1-10)Online publication date: Jan-2013
https://doi.org/10.1049/iet-cdt.2012.0103
Taskin BKourtev I(2006)Delay insertion method in clock skew schedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.87007225:4(651-663)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.870072
Taskin BKourtev IGroeneveld PScheffer L(2005)Delay insertion method in clock skew schedulingProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055149(47-54)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055149
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Index Terms

Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Published In

TAU '02: Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

December 2002

156 pages

ISBN:1581135262

DOI:10.1145/589411

General Chair:
David P. LaPotin
IBM
,
Program Chairs:
Charles J. Alpert
IBM
,
John Lillis
UIC

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Association for Computing Machinery

New York, NY, United States

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Published: 02 December 2002

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TAU02

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TAU02: International Workshop on Timing Issues in the Specifications and Synthesis of Digital Systems

December 2 - 3, 2002

California, Monterey, USA

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TAU '02 Paper Acceptance Rate 19 of 42 submissions, 45%;

Overall Acceptance Rate 19 of 42 submissions, 45%

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Cited By

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Broomhead DFurber SJohnson M(2013)Algebraic approach to time borrowingIET Computers & Digital Techniques10.1049/iet-cdt.2012.01037:1(1-10)Online publication date: Jan-2013
https://doi.org/10.1049/iet-cdt.2012.0103
Taskin BKourtev I(2006)Delay insertion method in clock skew schedulingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.87007225:4(651-663)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.870072
Taskin BKourtev IGroeneveld PScheffer L(2005)Delay insertion method in clock skew schedulingProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055149(47-54)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055149
Zhang LHu YChen CMalik SFix LKahng A(2004)Statistical timing analysis in sequential circuit for on-chip global interconnect pipeliningProceedings of the 41st annual Design Automation Conference10.1145/996566.996806(904-907)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996806
Taskin BKourtev I(2004)Advanced timing of level-sensitive sequential circuitsProceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.10.1109/ICECS.2004.1399753(603-606)Online publication date: 2004
https://doi.org/10.1109/ICECS.2004.1399753

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Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

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