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Design and evaluation of compiler algorithms for pre-execution

Published: 01 October 2002 Publication History
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  • Abstract

    Pre-execution is a promising latency tolerance technique that uses one or more helper threads running in spare hardware contexts ahead of the main computation to trigger long-latency memory operations early, hence absorbing their latency on behalf of the main computation. This paper investigates a source-to-source C compiler for extracting pre-execution thread code automatically, thus relieving the programmer or hardware from this onerous task. At the heart of our compiler are three algorithms. First, program slicing removes non-critical code for computing cache-missing memory references, reducing pre-execution overhead. Second, prefetch conversion replaces blocking memory references with non-blocking prefetch instructions to minimize pre-execution thread stalls. Finally, threading scheme selection chooses the best scheme for initiating pre-execution threads, speculatively parallelizing loops to generate thread-level parallelism when necessary for latency tolerance. We prototyped our algorithms using the Stanford University Intermediate Format (SUIF) framework and a publicly available program slicer, called Unravel [13], and we evaluated our compiler on a detailed architectural simulator of an SMT processor. Our results show compiler-based pre-execution improves the performance of 9 out of 13 applications, reducing execution time by 22.7%. Across all 13 applications, our technique delivers an average speedup of 17.0%. These performance gains are achieved fully automatically on conventional SMT hardware, with only minimal modifications to support pre-execution threads.

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      Published In

      cover image ACM Conferences
      ASPLOS X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
      October 2002
      318 pages
      ISBN:1581135742
      DOI:10.1145/605397
      • cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 30, Issue 5
        Special Issue: Proceedings of the 10th annual conference on Architectural Support for Programming Languages and Operating Systems
        December 2002
        296 pages
        ISSN:0163-5964
        DOI:10.1145/635506
        Issue’s Table of Contents
      • cover image ACM SIGOPS Operating Systems Review
        ACM SIGOPS Operating Systems Review  Volume 36, Issue 5
        December 2002
        296 pages
        ISSN:0163-5980
        DOI:10.1145/635508
        Issue’s Table of Contents
      • cover image ACM SIGPLAN Notices
        ACM SIGPLAN Notices  Volume 37, Issue 10
        October 2002
        296 pages
        ISSN:0362-1340
        EISSN:1558-1160
        DOI:10.1145/605432
        Issue’s Table of Contents
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      Published: 01 October 2002

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      • (2023)Decoupled Vector RunaheadProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614255(17-31)Online publication date: 28-Oct-2023
      • (2022)NURAProceedings of the ACM on Measurement and Analysis of Computing Systems10.1145/35080366:1(1-27)Online publication date: 28-Feb-2022
      • (2022)Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order CoresACM Transactions on Architecture and Code Optimization10.1145/350670419:2(1-28)Online publication date: 7-Mar-2022
      • (2022)Software pre-execution for irregular memory accesses in the HBM eraProceedings of the 31st ACM SIGPLAN International Conference on Compiler Construction10.1145/3497776.3517783(231-242)Online publication date: 19-Mar-2022
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      • (2019)BootstrappingProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304052(687-700)Online publication date: 4-Apr-2019
      • (2019)Freeway: Maximizing MLP for Slice-Out-of-Order Execution2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00009(558-569)Online publication date: Mar-2019
      • (2018)An Event-Triggered Programmable Prefetcher for Irregular WorkloadsACM SIGPLAN Notices10.1145/3296957.317318953:2(578-592)Online publication date: 19-Mar-2018
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