The Clipper processor: instruction set architecture and implementation

Reviewer: Trandafir Moisa

Although most readers are already familiar with the RISC versus CISC debates as one of the most interesting controversies of the last few years, it now seems we have a choice between a RISC, CLIPPER, or CISC architecture. This paper presents Intergraph's CLIPPER microprocessor, which is a high-performance, three-chip set that implements a new instruction set architecture. The architecture is very challenging and so is its presentation. However, it is not an easy task to cover such a complex microprocessor in only 20 pages. Even so, the paper presents schematic diagrams, instruction sets and their formats, and pure technological implementation restrictions like layout, chip area, and physical parameters. For readers interested in benchmarks and statistics, there are seven tables full of interesting results. The entire presentation focuses on the motivation and design philosophy of the CLIPPER C100 and C300 microprocessors. The authors' main design decisions and trade-offs come from their main goal, which is to design and build a chip set capable of achieving mainframe performance levels. These decisions are accompanied by a careful examination of the existing high-performance computers like CRAY machines, the IBM 801, and the DEC VAX. The most interesting lesson to be learned from this paper is that it is more reasonable to view RISC and CISC as implementation methodologies than as architectural constraints. CLIPPER falls somewhere between RISC and CISC and is more than an architecture with an efficient instruction set or an architecture that embodies high-semantic-content instructions like those implemented in Micro Instruction ROM. As a final point, do not miss the bibliography. It is extensive and consistent and, I am sure, very helpful.