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A cache coherence scheme with fast selective invalidation

Authors:

A. V. VaidenbaumAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 16, Issue 2

Pages 299 - 307

https://doi.org/10.1145/633625.52434

Published: 17 May 1988 Publication History

Abstract

Software-assisted cache coherence enforcement schemes for large multiprocessor systems with shared global memory and interconnection network have gained increasing attention. Proposed software-assisted approaches rely on either indiscriminate invalidation or selective invalidation to invalidate stale cache lines. The indiscriminate approach combined with advanced memory hardware can quickly invalidate the entire cache but may result in lower hit ratios. The selective approach may achieve a better hit ratio. However, sequential selection and invalidation of cache or TLB entries is time consuming. We propose a new solution that offers the fast operation of the indiscriminate invalidation approach and can selectively invalidate cache items without extensive run-time book-keeping and checking. The solution relies on the combination of compile-time reference tagging and individual invalidation of potentially stale cache lines only when referenced. Performance improvement over an indiscriminate invalidation approach is presented.

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Cited By

Choi LYew P(2000)Hardware and Compiler-Directed Cache Coherence in Large-Scale MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.85083411:4(375-394)Online publication date: 1-Apr-2000
https://dl.acm.org/doi/10.1109/71.850834
Mounes-Toussi FLilja D(1994)Performance Limits of Compiler-Directed Multiprocessor Cache Coherence EnforcementThe Interaction of Compilation Technology and Computer Architecture10.1007/978-1-4615-2684-1_7(161-190)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2684-1_7
Cheong HKennedy KPolychronopoulos C(1992)Life span strategy—a compiler-based approach to cache coherenceProceedings of the 6th international conference on Supercomputing10.1145/143369.143402(139-148)Online publication date: 1-Aug-1992
https://dl.acm.org/doi/10.1145/143369.143402
Show More Cited By

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A cache coherence scheme with fast selective invalidation

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 16, Issue 2

Special Issue: Proceedings of the 15th annual international symposium on Computer Architecture

May 1988

431 pages

ISSN:0163-5964

DOI:10.1145/633625

Issue’s Table of Contents

ISCA '88: Proceedings of the 15th Annual International Symposium on Computer architecture
June 1988
461 pages
ISBN:0818608617
Chairman:
H. J. Siegel
Purdue Univ., West Lafayette, IN

Copyright © 1988 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 May 1988

Published in SIGARCH Volume 16, Issue 2

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Cited By

Choi LYew P(2000)Hardware and Compiler-Directed Cache Coherence in Large-Scale MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.85083411:4(375-394)Online publication date: 1-Apr-2000
https://dl.acm.org/doi/10.1109/71.850834
Mounes-Toussi FLilja D(1994)Performance Limits of Compiler-Directed Multiprocessor Cache Coherence EnforcementThe Interaction of Compilation Technology and Computer Architecture10.1007/978-1-4615-2684-1_7(161-190)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2684-1_7
Cheong HKennedy KPolychronopoulos C(1992)Life span strategy—a compiler-based approach to cache coherenceProceedings of the 6th international conference on Supercomputing10.1145/143369.143402(139-148)Online publication date: 1-Aug-1992
https://dl.acm.org/doi/10.1145/143369.143402
AL-SADOUN HABDUL-LATEEF H(1992)Cache coherency in multiple bus systemsInternational Journal of Electronics10.1080/0020721920892568573:3(497-522)Online publication date: Sep-1992
https://doi.org/10.1080/00207219208925685
Lai FWu CParng TPapachristou CAllan V(1990)A memory management unit and cache controller for the MARS systemProceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture10.5555/255237.255276(200-208)Online publication date: 30-Nov-1990
https://dl.acm.org/doi/10.5555/255237.255276
Gutierrez APusdesris JDreslinski RMudge TJerraya ACarloni LMooney VRabbah R(2012)Lazy cache invalidation for self-modifying codesProceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems10.1145/2380403.2380433(151-160)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380403.2380433
Tarjan DSkadron KHess B(2010)The Sharing TrackerProceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis10.1109/SC.2010.54(1-10)Online publication date: 13-Nov-2010
https://dl.acm.org/doi/10.1109/SC.2010.54
Wang HLi KLu SYang CGaudiot J(2008)Design and implementation of an agent home scheme strategy for prefetch-based DSM systemsInternational Journal of Parallel Programming10.1007/s10766-007-0069-736:6(521-542)Online publication date: 1-Dec-2008
https://dl.acm.org/doi/10.1007/s10766-007-0069-7
Choi LYew P(2000)Hardware and Compiler-Directed Cache Coherence in Large-Scale MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.85083411:4(375-394)Online publication date: 1-Apr-2000
https://dl.acm.org/doi/10.1109/71.850834
Giorgi RPrete C(1999)PSCRIEEE Transactions on Parallel and Distributed Systems10.1109/71.78086810:7(742-763)Online publication date: 1-Jul-1999
https://dl.acm.org/doi/10.1109/71.780868
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