Multiple vs. wide shared bus multiprocessors
Authors: 
A. Hopper, A. Jones, D. LioupisAuthors Info & Claims
A. Hopper, A. Jones, D. LioupisAuthors Info & ClaimsPages 300 - 306
Abstract
In this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement.
We have simulated a number of configurations in order to assess the relative performance of multiple versus wide bus machines, with varying amounts of prefetch. Four programs, with widely differing characteristics, were run on each configuration. The configurations that gave the best all-round results were multiple narrow buses with 4 words of prefetch.
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Multiple vs. wide shared bus multiprocessors
ISCA '89: Proceedings of the 16th annual international symposium on Computer architectureIn this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement.
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Copyright © 1989 Authors.
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Association for Computing Machinery
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Published: 01 April 1989
Published in SIGARCH Volume 17, Issue 3
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