article

Free access

Fault-secure algorithms for multiple-processor systems

Authors:

Prithviraj Banerjee,

Jacob A. AbrahamAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 12, Issue 3

Pages 279 - 287

https://doi.org/10.1145/773453.808196

Published: 01 January 1984 Publication History

Abstract

In this paper we describe techniques for achieving fault secureness with low cost in multiple processor⁷ systems. In order to do this we consider the relationships_N between algorithms, parallel architectures, and fault tolerance. The concept of fault-secure algorithms, described in this paper, involves the application of the ideas of fault tolerance at the system level to high-performance multiple-processor algorithms to make the results of the computation reliable. Algorithms are classified into broad classes called paradigms which are determined exclusively by the communication patterns of the processors. Fault-secure techniques are presented for three powerful paradigms: the multiplex, the recursive combination, and the multiplex-demultiplex paradigms. The basic idea used in the design of fault-tolerant algorithms is that the algorithms operate on encoded input data and produce encoded output data such that the over-head in time and number of processors is not high. This technique is distinguished by three characteristics: the encoding of the data used by the algorithm, the re-design of the algorithm to operate on the encoded data, and the distribution of the computation steps in the algorithm among the computation units.

References

[1]

A. V. Aho, J. E. Hopcroft, and J. D. Ullman,The Design and Analysis of Computer Algorithms, Addison-Wesley, Reading, Mass., 1974.

Digital Library

[2]

D. A. Anderson, Design of Self-Checking Digital Networks Using Coding Techniques, Tech. Rep. R-527, Coordinated Sci. Lab., Univ. of Illinois, Urbana, Sept. 1971.

[3]

P. Banerjee and J. A. Abraham, "Fault Characterization of VLSI MOS Circuits," Proc. IEEE Int. Conf. on Circuits and Computers, New York, NY, Sept. 1982, pp. 564-568.

[4]

C. C. Beh, K. H. Arya, C. E. Radke, and K. E. Torku, "Do Stuck-At Fault Models Reflect Manufacturing Defects?" Proc. Int. Test Conf., Cherry Hill, Philadelphia, PA, Nov. 82.

[5]

G. H. Barnes, R. M. Brown, M. Kato, D. J. Kuck, D. J. Slotnick, and R. A. Stokes, "The ILLIAC IV Computer," IEEE Trans. on Computers, vol. C-17, Aug. 1968, pp. 746-757.

[6]

K. E. Batcher, "Sorting Networks and Their Applications," Proc. A.F.I.P.S. Spring Joint Comp. Conf., April 1968, vol. 32, pp. 307-314.

[7]

K. E. Batcher, "Design of a Massively Parallel Processor," IEEE Trans. on Computers, vol. C-29, no. 9, Sept. 1980, pp. 836-840.

[8]

R. P. Brent, "The Parallel Evaluation of General Arithmetic Expressions," Jour. Assoc. Comp. Mach., vol. 21, no. 2, April 1974, pp. 201-206.

Digital Library

[9]

K. Y. Chwa and S. L. Hakimi,"Schemes for Fault-Tolerant Computing: A Comparison of Modularly Redundant and t-Diagnosable Systems," Information and Control, vol. 49, no. 3, June 1981, pp. 212-238.

[10]

D. Fussell and P. Varman, "Fault-Tolerant Wafer-Scale Architectures for VLSI," Proc. 9th Annual Symp. on Computer Architecture, April 1982, Austin, TX, pp. 190-198.

Digital Library

[11]

J. P. Hayes, "A Graph Model for Fault-Tolerant Computing Systems," IEEE Trans. Computers, vol C-25, no. 9, Sep. 1976, pp. 875-884.

[12]

K. H. Huang and J. A. Abraham, "Low Cost Schemes for Fault Tolerance in Matrix Operations With Processor Arrays," Proc. 12th Int. Symp. on Fault-Tolerant Computing, Santa Monica, CA, June 1982.

[13]

K. H. Huang and J. A. Abraham, "Algorithm-based Fault Tolerance for Matrix Operations," IEEE Trans. on Computers, vol. C-33, July 1984 (to appear).

[14]

I. Koren, "A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array," Proc. 8th Annual Symp. on Computer Architecture, Minneapolis, MN, May 1981, pp. 425-442.

Digital Library

[15]

D. J. Kuck, The Structure of Computers and Computation, Vol. I, John Wiley and Sons, New York, 1978.

Digital Library

[16]

H. T. Kung, "Let's Design Algorithms for VLSI systems," Proc. Conference on Very Large Scale Integration: Architecture, Design, Fabrication, California Institute of Technology, Pasadena, CA, Jan. 1979.

[17]

D. J. Kuck and R. A. Stokes, "The Burroughs Scientific Processor (BSP)," IEEE Trans. on Computers, vol. C-31, no. 5, May 1982, pp. 363-376.

[18]

S. Laha and J. H. Patel, "Error Correction for Arithmetic Operations Using Time Redundancy," Proc. 13th Int. Symp. on Fault-Tolerant Computing, Milan, Italy, June 1983, pp. 298-305.

[19]

F. T. Leighton, "New Lower Bound Techniques for VLSI," Proc. 22nd IEEE Symp. on Found. Comp. Sci., Nashville, TN, Oct. 1981, pp. 1-21.

[20]

D. E. Muller and F. P. Preparata, "Bounds to Complexities of Networks for Sorting and for Switching," Jour. Assoc. Comp. Mach., vol. 22, no. 2, April 1975, pp. 195-201.

Digital Library

[21]

I. Munro and M. Paterson, "Optimal Algorithms for Parallel Polynomial Evaluation," Jour. Comp. Sys. Sci., vol. 7, 1973, pp. 189-198.

Digital Library

[22]

J. Von Neumann, "Probabilistic Logics and The Synthesis of Reliable Organisms From Unreliable Components," Automata Studies, no. 34, 1956, Princeton, NJ, Princeton Univ. Press Ann. of Math. Studies, pp. 43-99.

[23]

A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1975, pp. 290-299.

Digital Library

[24]

J. H. Patel and L. Y. Fung, "Concurrent Error Detection in ALUs by Recomputing With Shifted Operands," IEEE Trans. on Computers, vol. C-31, no. 7, July 1982, pp. 589-595.

[25]

L. H. Pollard and J. H. Patel, "Correction of Errors in Data Transmission Using Time Redundancy," Proc. 13th Int. Symp. on Fault-Tolerant Computing, Milan, Italy, June 1983, pp. 314-317.

[26]

F. P. Preparata, "Algorithm Design and VLSI Architectures," Proc. Symp. on Vector Processors and Scientific Computation, Rome, Italy, Mar. 1982.

[27]

F. P. Preparata and J. Vuillemin, "The Cube-Connected Cycles: A Versatile Network For Parallel Computation," Comm. Assoc. of Comp. Mach., vol. 24, no. 5, May 1981, pp. 300-309.

Digital Library

[28]

F. P. Preparata and J. Vuillemin, "Area-Time Optimal VLSI Networks for Computing Integer Multiplication and Discrete Fourier Transform," Proc. of I.C.A.L.P., Acre, Israel, July 1981.

Digital Library

[29]

E. Reghbati (Arjomandi) and D. G. Cornell, "Parallel Computations in Graph Theory," SIAM Jour. Computing, vol. 7, no. 2, May 1978.

[30]

D. A. Reynolds and G. Metze, "Fault Detection Capabilities of Alternating Logic," IEEE Trans. on Computers, Dec. 1978, pp. 1093-1098.

Digital Library

[31]

R. J. Swan, S. H. Fuller, and D. P. Siewiorek, "Cm* - A Modular Multi-microprocessor," Proc. of the National Computer Conference, vol 466, 1977, pp. 637-644.

[32]

J. G. Tryon, "Quadded Logic," Redundancy Techniques for Computing Systems, Wilcox and Mann, ed., Washington, D. C., Spartan Books, 1962, pp. 205-228.

[33]

L. C. Widdoes, Jr. and S. Correll, "The S-1 Project: Developing High-Performance Digital Computers," Energy and Technology Review, Lawrence Livermore Laboratory Press, Sept. 1979.

[34]

J. H. Wensley, L. Lamport, J. Goldberg, M. W. Green, K. N. Levitt, P. M. Melliar-Smith, R. E. Shostak, and C. B. Weinstock, "SIFT: Design and Analysis of a Fault-Tolerant Computer for Aircraft Control," Proc. of the IEEE, vol. 66, no. 10, Oct. 1978, pp. 1240-1255.

Cited By

Wu J(2017)Static Load DistributionDistributed System Design10.1201/9781315141411-9(301-351)Online publication date: 14-Dec-2017
https://doi.org/10.1201/9781315141411-9
Wu KKarri R(2006)Fault secure datapath synthesis using hybrid time and hardware redundancyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83513223:10(1476-1485)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.835132
Ghosh SRajkumar RHansen JLehoczky J(2003)Scalable resource allocation for multi-processor QoS optimization23rd International Conference on Distributed Computing Systems, 2003. Proceedings.10.1109/ICDCS.2003.1203464(174-183)Online publication date: 2003
https://doi.org/10.1109/ICDCS.2003.1203464
Show More Cited By

Index Terms

Fault-secure algorithms for multiple-processor systems
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Hardware test
  2. Robustness

Recommendations

Fault-secure algorithms for multiple-processor systems
ISCA '84: Proceedings of the 11th annual international symposium on Computer architecture

In this paper we describe techniques for achieving fault secureness with low cost in multiple processor⁷ systems. In order to do this we consider the relationships_N between algorithms, parallel architectures, and fault tolerance. The concept of fault-...
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems
The MIT Press scientific computation series

An important consideration in the design of high- performance multiple processor systems should be in ensuring the correctness of results computed by such complex systems which are extremely prone to transient and intermittent failures. The detection ...
Fault Tolerance in Multiprocessor Systems Without Dedicated Redundancy

An algorithm called RAFT (recursive algorithm for fault tolerance) for achieving fault tolerance in multiprocessor systems is described. Through the use of a combination of dynamic space- and time- redundancy techniques, RAFT achieves fault tolerance in ...

Comments

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 12, Issue 3

June 1984

348 pages

ISSN:0163-5964

DOI:10.1145/773453

Issue’s Table of Contents

ISCA '84: Proceedings of the 11th annual international symposium on Computer architecture
January 1984
373 pages
ISBN:0818605383
DOI:10.1145/800015
Chairman:
Dharma P. Agrawal

Copyright © 1984 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 January 1984

Published in SIGARCH Volume 12, Issue 3

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

29
Total Citations
View Citations
513
Total Downloads

Downloads (Last 12 months)53
Downloads (Last 6 weeks)13

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wu J(2017)Static Load DistributionDistributed System Design10.1201/9781315141411-9(301-351)Online publication date: 14-Dec-2017
https://doi.org/10.1201/9781315141411-9
Wu KKarri R(2006)Fault secure datapath synthesis using hybrid time and hardware redundancyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83513223:10(1476-1485)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.835132
Ghosh SRajkumar RHansen JLehoczky J(2003)Scalable resource allocation for multi-processor QoS optimization23rd International Conference on Distributed Computing Systems, 2003. Proceedings.10.1109/ICDCS.2003.1203464(174-183)Online publication date: 2003
https://doi.org/10.1109/ICDCS.2003.1203464
Karri RIyer B(2001)IntrospectionACM Transactions on Design Automation of Electronic Systems10.1145/502175.5021796:4(501-515)Online publication date: 1-Oct-2001
https://dl.acm.org/doi/10.1145/502175.502179
Orailoglu AKarri R(1996)Automatic Synthesis of Self-Recovering VLSI SystemsIEEE Transactions on Computers10.1109/12.48536845:2(131-142)Online publication date: 1-Feb-1996
https://dl.acm.org/doi/10.1109/12.485368
Abraham JMetze GIyer RPatel J(1987)The Evolution of Fault Tolerant Computing at the University of IllinoisThe Evolution of Fault-Tolerant Computing10.1007/978-3-7091-8871-2_11(271-288)Online publication date: 1987
https://doi.org/10.1007/978-3-7091-8871-2_11
Trobec RJerebic I(2005)Optimization of diagnostic examinationParallel Processing: CONPAR 94 — VAPP VI10.1007/3-540-58430-7_66(761-772)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-58430-7_66
Trobec R(2005)Cellular diagnostic in parallel systemsParcella '8810.1007/3-540-50647-0_130(360-365)Online publication date: 2-Jun-2005
https://doi.org/10.1007/3-540-50647-0_130
Iyer RSanders WPatel JKalbarczyk Z(2004)The Evolution of Dependable Computing at the University of IllinoisBuilding the Information Society10.1007/978-1-4020-8157-6_15(135-164)Online publication date: 2004
https://doi.org/10.1007/978-1-4020-8157-6_15
Ghosh SRajkumar RHansen JLehoczky J(2003)Scalable Resource Allocation for Multi-Processor QoS OptimizationProceedings of the 23rd International Conference on Distributed Computing Systems10.5555/850929.851961Online publication date: 19-May-2003
https://dl.acm.org/doi/10.5555/850929.851961
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents