Article

Implicit treatment of substrate and power-ground losses in return-limited inductance extraction

Authors:

K. L. ShepardAuthors Info & Claims

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Pages 16 - 22

https://doi.org/10.1145/774572.774575

Published: 10 November 2002 Publication History

Abstract

Full-wave analysis, based on rigorous solution of the differential or integral form of Maxwell's equations, is too slow for all but the smallest designs. Traditional on-chip extraction engines are, therefore, being pushed to extract inductance and provide accurate high-frequency interconnect modelling while maintaining computational efficiency and capacity. This paper describes further accuracy-improving enhancements to the commecial full-chip RLCK extraction engine, Assura RLCX[1], based on the return-limited inductance formulation. Specifically, we incorporate substrate losses due to eddy currents and power-ground losses while, based on design-driven assumptions, avoiding explicit extraction of the power-ground and substrate. Results are validated on small testcases where comparison with full-wave solution is practical.

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Cited By

Dima MBecks K(2006)Digital-noise reduction with on-chip/module inductorsNuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment10.1016/j.nima.2005.11.224558:2(554-560)Online publication date: Mar-2006
https://doi.org/10.1016/j.nima.2005.11.224
Ji HYu QDai WImai M(2004)SPICE compatible circuit models for partial reluctance KProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015301(786-791)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015301
Lescot JClément F(2003)Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated CircuitsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-39762-5_12(101-110)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39762-5_12

Index Terms

Implicit treatment of substrate and power-ground losses in return-limited inductance extraction

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cover image ACM Conferences

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

November 2002

793 pages

ISBN:0780376072

DOI:10.1145/774572

General Chair:
Lawrence T. Pileggi
Carnegie Mellon Univ., Pittsburgh, PA
,
Program Chair:
Andreas Kuehlmann
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2002 ACM.

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Publication History

Published: 10 November 2002

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ICCAD02: 2002 IEEE / ACM International Conference on Computer Aided Design

November 10 - 14, 2002

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Cited By

Dima MBecks K(2006)Digital-noise reduction with on-chip/module inductorsNuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment10.1016/j.nima.2005.11.224558:2(554-560)Online publication date: Mar-2006
https://doi.org/10.1016/j.nima.2005.11.224
Ji HYu QDai WImai M(2004)SPICE compatible circuit models for partial reluctance KProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015301(786-791)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015301
Lescot JClément F(2003)Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated CircuitsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-39762-5_12(101-110)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39762-5_12

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