Article

Coupling-aware high-level interconnect synthesis for low power

Authors:

Ki-Wook KimAuthors Info & Claims

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Pages 609 - 613

https://doi.org/10.1145/774572.774662

Published: 10 November 2002 Publication History

Abstract

Ultra deep submicron (UDSM) technology and system-on-chip (SoC) have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are (1) the transition activities on the signal lines and (2) the coupling capacitances of the lines. However, there has been no easy way of optimizing (1) and (2) simultaneously at an early stage of the synthesis process. In this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of (1) and (2) in the microarchitecture synthesis. Specifically, unlike the previous approaches in which (1) and (2) are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled dataflow graph to be synthesized, minimize (1) and (2) simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of (1) and (2). Experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3% and 18.1% on average over those in [12] (for minimizing (1) only), [1] (for (2) only) and [12, 1] (for (1) and then (2)), respectively.

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Cited By

Moiseev KKolodny AWimer S(2008)Timing-aware power-optimal ordering of signalsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197313:4(1-17)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391973
Pasricha SDutt N(2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00006-2
Lim KKim YKim TLevitan S(2007)Interconnect and communication synthesis for distributed register-file microarchitectureProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278672(765-770)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278672
Show More Cited By

Index Terms

Coupling-aware high-level interconnect synthesis for low power

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Ultra-deep submicron technology and system-on-chip have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are: 1) the self transition activities on the signal lines and 2) the coupled ...

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cover image ACM Conferences

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

November 2002

793 pages

ISBN:0780376072

DOI:10.1145/774572

General Chair:
Lawrence T. Pileggi
Carnegie Mellon Univ., Pittsburgh, PA
,
Program Chair:
Andreas Kuehlmann
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 November 2002

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ICCAD02: 2002 IEEE / ACM International Conference on Computer Aided Design

November 10 - 14, 2002

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Citations

Cited By

Moiseev KKolodny AWimer S(2008)Timing-aware power-optimal ordering of signalsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197313:4(1-17)Online publication date: 3-Oct-2008
https://dl.acm.org/doi/10.1145/1391962.1391973
Pasricha SDutt N(2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00006-2
Lim KKim YKim TLevitan S(2007)Interconnect and communication synthesis for distributed register-file microarchitectureProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278672(765-770)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278672
Murgan TBacinschi POrtiz AGlesner M(2006)Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitanceProceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/11847083_17(169-180)Online publication date: 13-Sep-2006
https://dl.acm.org/doi/10.1007/11847083_17
García-Ortiz AMurgan TGlesner M(2004)Moment-Based Estimation of Switching Activity for Correlated DistributionsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-30205-6_88(859-868)Online publication date: 2004
https://doi.org/10.1007/978-3-540-30205-6_88
Garcia-Ortiz AKabulepa LMurgan TGlesner M(2003)Moment-Based Power Estimation in Very Deep Submicron TechnologiesProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009877Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009877
Garcia-Ortiz AKabulepa LMurgan TGlesner M(2003)Moment-based power estimation in very deep submicron technologiesICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)10.1109/ICCAD.2003.159678(107-112)Online publication date: 2003
https://doi.org/10.1109/ICCAD.2003.159678

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