Article

Improved indexing for cache miss reduction in embedded systems

Author:

Tony GivargisAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 875 - 880

https://doi.org/10.1145/775832.776052

Published: 02 June 2003 Publication History

Abstract

The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved performance. In traditional cache design, the index portion of the memory address bus consists of the K least significant bits, where K=log2(D) and D is the depth of the cache. However, in devices where the application set is known and characterized (e.g., systems that execute a fixed application set) there is an opportunity to improve cache performance by choosing an optimal set of bits used as index into the cache. This technique does not add any overhead in terms of area or delay. We give an efficient heuristic algorithm for selecting K index bits for improved cache performance. We show the feasibility of our algorithm by applying it to a large number of embedded system applications as well as the integer SPEC CPU 2000 benchmarks.

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Cited By

Garzón EHanhan RLanuzza MTeman AYavits L(2024)FASTA: Revisiting Fully Associative Memories in Computer MicroarchitectureIEEE Access10.1109/ACCESS.2024.335596112(13923-13943)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3355961
Ho NKaufmann PPlatzner M(2020)Evolution of application-specific cache mappingsInternational Journal of Hybrid Intelligent Systems10.3233/HIS-200281(1-13)Online publication date: 3-Jul-2020
https://doi.org/10.3233/HIS-200281
Mosquera FGulur NKavi KMehta GSun H(2020)CHASM: Security Evaluation of Cache Mapping SchemesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_17(245-261)Online publication date: 7-Oct-2020
https://doi.org/10.1007/978-3-030-60939-9_17
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Index Terms

Improved indexing for cache miss reduction in embedded systems
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Garzón EHanhan RLanuzza MTeman AYavits L(2024)FASTA: Revisiting Fully Associative Memories in Computer MicroarchitectureIEEE Access10.1109/ACCESS.2024.335596112(13923-13943)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3355961
Ho NKaufmann PPlatzner M(2020)Evolution of application-specific cache mappingsInternational Journal of Hybrid Intelligent Systems10.3233/HIS-200281(1-13)Online publication date: 3-Jul-2020
https://doi.org/10.3233/HIS-200281
Mosquera FGulur NKavi KMehta GSun H(2020)CHASM: Security Evaluation of Cache Mapping SchemesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-60939-9_17(245-261)Online publication date: 7-Oct-2020
https://doi.org/10.1007/978-3-030-60939-9_17
Ho NKaufmann PPlatzner M(2020)Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 ProcessorProceedings of the 11th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2019)10.1007/978-3-030-49345-5_28(266-276)Online publication date: 1-Aug-2020
https://doi.org/10.1007/978-3-030-49345-5_28
Shatnawi AAlsaedeen M(2018)Reducing the second-level cache conflict misses using a set folding techniqueThe Journal of Supercomputing10.1007/s11227-017-2174-874:2(970-993)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s11227-017-2174-8
Han FLi LWang KFeng FPan HSha JLin J(2017)An access pattern based adaptive mapping function for GPGPU scratchpad memoryIEICE Electronics Express10.1587/elex.14.2017037314:12(20170373-20170373)Online publication date: 2017
https://doi.org/10.1587/elex.14.20170373
Choo KTroendle DGad EJang B(2017)Contention-Aware Selective Caching to Mitigate Intra-Warp Contention on GPUs2017 16th International Symposium on Parallel and Distributed Computing (ISPDC)10.1109/ISPDC.2017.17(1-8)Online publication date: Jul-2017
https://doi.org/10.1109/ISPDC.2017.17
Ho NKaufmann PPlatzner M(2017)Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280144(215-218)Online publication date: Dec-2017
https://doi.org/10.1109/FPT.2017.8280144
Kaufmann PHo NPlatzner M(2017)Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2017.8046380(206-213)Online publication date: Jul-2017
https://doi.org/10.1109/AHS.2017.8046380
Panda P(2017)Memory ArchitecturesHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_14-1(1-31)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_14-1
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