Article

Crosstalk noise in FPGAs

Authors:

Yajun Ran,

Malgorzata Marek-SadowskaAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 944 - 949

https://doi.org/10.1145/775832.776069

Published: 02 June 2003 Publication History

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Abstract

In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune to crosstalk noise than their ASIC counterparts manufactured in the same technological process, we have reached the point where FPGAs have become affected by crosstalk as well. Because FPGAs have regular interconnect structures, crosstalk noise can be more easily controlled. In this paper, we investigate the crosstalk noise in FPGAs and propose new strategies to reduce its impact on delay. Our methods can reduce crosstalk noise by statistically significant amounts with no penalty in performance, power, or area.

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Cited By

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Giechaskiel IEguro KRasmussen K(2019)Leakier WiresACM Transactions on Reconfigurable Technology and Systems10.1145/332248312:3(1-29)Online publication date: 23-Aug-2019
https://dl.acm.org/doi/10.1145/3322483
Giechaskiel IRasmussen KEguro KKim JAhn GKim SKim YLopez JKim T(2018)Leaky WiresProceedings of the 2018 on Asia Conference on Computer and Communications Security10.1145/3196494.3196518(15-27)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3196494.3196518
Das NRoy PRahaman H(2014)Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)Journal of The Institution of Engineers (India): Series B10.1007/s40031-014-0141-996:3(227-236)Online publication date: 15-Jul-2014
https://doi.org/10.1007/s40031-014-0141-9
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Index Terms

Crosstalk noise in FPGAs
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Giechaskiel IEguro KRasmussen K(2019)Leakier WiresACM Transactions on Reconfigurable Technology and Systems10.1145/332248312:3(1-29)Online publication date: 23-Aug-2019
https://dl.acm.org/doi/10.1145/3322483
Giechaskiel IRasmussen KEguro KKim JAhn GKim SKim YLopez JKim T(2018)Leaky WiresProceedings of the 2018 on Asia Conference on Computer and Communications Security10.1145/3196494.3196518(15-27)Online publication date: 29-May-2018
https://dl.acm.org/doi/10.1145/3196494.3196518
Das NRoy PRahaman H(2014)Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)Journal of The Institution of Engineers (India): Series B10.1007/s40031-014-0141-996:3(227-236)Online publication date: 15-Jul-2014
https://doi.org/10.1007/s40031-014-0141-9
Yu JLai JChow PCheung P(2009)A novel minloop SB design to improve FPGA routabilityProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508202(286-286)Online publication date: 24-Feb-2009
https://dl.acm.org/doi/10.1145/1508128.1508202
Omaña MCazeaux JRossi DMetra CGielen G(2006)Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnectsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131533(170-175)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131533
Schmit HChandra V(2005)Layout techniques for FPGA switch blocksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.84040213:1(96-105)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1109/TVLSI.2004.840402

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Reduced thickness interconnect model using GNR to avoid crosstalk effects

Crosstalk noise reduction in synthesized digital logic circuits

Noise in deep submicron digital design

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Recommendations

Reduced thickness interconnect model using GNR to avoid crosstalk effects

Crosstalk noise reduction in synthesized digital logic circuits

Noise in deep submicron digital design

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