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Designing algorithms on hierarchical memory multiprocessors

Published: 01 June 1990 Publication History

Abstract

We study here the behavior of two numerical algorithms (matrix multiplications and finite difference methods) on a three-level memory hierarchy multiprocessor RP3. Using different versions of these algorithms which differ on data placement (global, local, global and cacheable, local and cacheable) and on data access (blocked on non-blocked), we study the impact of these parameters on the performance of the program. This performance analysis is done using a very accurate monitoring system (VPMC) which records instructions, memory requests, cache requests and misses. We perform also a theoretical performance analysis of these programs using a model of computation and communication. Good agreements are found between theoretical and experimental results. As a conclusion we discuss the use of local memory on such a machine and show it is not worth with the RP3 ratio of communication between local and global memories. We also discuss optimal use of cache, show the optima can only be met under some cache properties (private store-in cache with user control of write-back) and show blocked optimal algorithms are to be used to meet it.

References

[1]
W. C. Brantley and H. Y. Chang, "Support Environment for RP3 Performance Monitor," in M. Simmons, R. Koskela, and !. Bucher, Ed. Performance Instrumentation and Visualization for Parallel Computer Systems, Addison-Wesley, (I 990).
[2]
W. C. Brantley, K. P. McAuliffe, and T. A. Ngo, "RP3 Performance Monitoring Hardware," in M. Simmons, R. Koskela, and I. Bucher, Ed. Instrumentation for Parallel Computer Systems, 35-47, Addison-Wesley, (1989).
[3]
W. C. Brantley, K. P. McAuliffe, and J. Weiss, "RP3 Processor-Memory Element," Proceedings of the 1985 International Conference on Parallel Processing, 782-789, (1985).
[4]
L. Brochard, "Efficiency of some numerical algorithms on distributed systems," Parallel Computing, 12, 21-44, (1989),
[5]
L. Brochard, "Scalability, granularity and parallelism of numerical algorithms," RC 14786, IBM Research Report, 1989.
[6]
L. Brochard and A. Freau, "Computation and data movement on RP3.," RC 15231, IBM Research Report, 1989.
[7]
L. Brochard and A. Freau, "Designing Algorithms on Hierarchical Memory Multiprocessors.," RC 15271, IBM Research Report, 1989.
[8]
W.L. Brochard, K. J. P. Prost, and F. Faurie, "Synchronization and load unbalance effects of parallel iterative algorithms," Proceedings of the 1989 International Conference on Parallel Processing, ili, 153-160, (1989).
[9]
G.C. Fox, "Domain decomposition in distributed and shared memory environments," in E. Housds, T.S. Papatheodorou, and C.D. Polychronopoulos, Ed. Proceedings of Supercomputing 87, 1042-1073., Lecture Notes in Computer Science 297, Springer-Verlag, (1988).
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G. Fox, M. Johnson, G. Lyzenga, S. Otto, J. Salmon, and D. Walker, Solving problems on concurrent processors. Vol t, Prentice Hall, 1988.
[11]
K. Gallivan, W. Jalby, U. Meier, and A. Sameh, "The impact of hierarchical memory systems on linear algebra algorithm design," Int. J. of Super. Appl., 2, No. I, 12-48, (1988).
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D. Marinescu and J. Rice, "On the effects of synchronization in parallel computing," CSD-TR-750, Purdue Univ., 1988.
[13]
G.F. Pfister, W. C. Brantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. P. McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss, "The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture," Proceedings of the 1985 International Conference on Parallel Processing, 764-771, (1985).
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K. Solchenbach, "Grid applications on distributed memory architectures: Implementation and evaluation," Parallel Computing, 7, No. 3, 341-356, (1988).

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  • (1991)Beyond loop partitioningProceedings of the 5th international conference on Supercomputing10.1145/109025.109074(172-182)Online publication date: 1-Jun-1991

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cover image ACM Conferences
ICS '90: Proceedings of the 4th international conference on Supercomputing
June 1990
492 pages
ISBN:0897913698
DOI:10.1145/77726
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 18, Issue 3b
    Special Issue: Proceedings of the 4th international conference on Supercomputing
    Sept. 1990
    489 pages
    ISSN:0163-5964
    DOI:10.1145/255129
    Issue’s Table of Contents
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Published: 01 June 1990

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IC'90: ACM SIGARCH International Conference on Supercomputing
June 11 - 15, 1990
Amsterdam, The Netherlands

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  • (1991)Beyond loop partitioningProceedings of the 5th international conference on Supercomputing10.1145/109025.109074(172-182)Online publication date: 1-Jun-1991

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