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An integrated mask artwork analysis system

Authors:

Takashi Mitsuhashi,

Toshiaki Chiba,

Makoto Takashima, and

Kenji YoshidaAuthors Info & Claims

DAC '80: Proceedings of the 17th Design Automation Conference

June 1980

Pages 277 - 284

https://doi.org/10.1145/800139.804540

Published: 23 June 1980 Publication History

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Abstract

A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.

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Cited By

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Bales M(2016)Design DatabasesElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-17(349-371)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-17
Mitsuhashi TYoshida K(2006)A Resistance Calculation Algorithm and Its Application to Circuit ExtractionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1987.12702786:3(337-345)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.1987.1270278
Szymanski TVan Wyk C(2003)GOALIE: A Space-Efficient System for VLSI Artwork AnalysisThe Best of ICCAD10.1007/978-1-4615-0292-0_38(489-497)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-0292-0_38
Show More Cited By

Index Terms

An integrated mask artwork analysis system
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits

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The timing simulator MACTIS was successfully applied to functional verification of MOS memory circuits from mask artwork data. The circuit description is extracted automatically from artwork data by the mask analysis program. Combining the macromodel ...
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Published In

DAC '80: Proceedings of the 17th Design Automation Conference

June 1980

642 pages

ISBN:0897910206

DOI:10.1145/800139

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 1980

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Bales M(2016)Design DatabasesElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-17(349-371)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-17
Mitsuhashi TYoshida K(2006)A Resistance Calculation Algorithm and Its Application to Circuit ExtractionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1987.12702786:3(337-345)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.1987.1270278
Szymanski TVan Wyk C(2003)GOALIE: A Space-Efficient System for VLSI Artwork AnalysisThe Best of ICCAD10.1007/978-1-4615-0292-0_38(489-497)Online publication date: 2003
https://doi.org/10.1007/978-1-4615-0292-0_38
Takashima MIkeuchi AKojima STanaka TSaitou TSakata JShaklee DNewton A(1988)A circuit comparison system with rule-based functional isomorphism checkingProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285813(512-516)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285813
Song HTang P(1988)A new approach for circuit extraction based on overlay graph1988., IEEE International Symposium on Circuits and Systems10.1109/ISCAS.1988.15202(1449-1452)Online publication date: 1988
https://doi.org/10.1109/ISCAS.1988.15202
Saito TYamamoto TShigematsu TNagao KTakeda SSuzuki YWinkler SStone H(1986)Advanced super integrationProceedings of 1986 ACM Fall joint computer conference10.5555/324493.325019(1008-1013)Online publication date: 2-Nov-1986
https://dl.acm.org/doi/10.5555/324493.325019
Xianlong HShu XQinglin XLongbao Z(1986)AN LSI MASK ARTWORK VERIFICATION AND PROCESSING SYSTEM JC—81Control Science and Technology for Development10.1016/B978-0-08-033473-8.50049-8(253-256)Online publication date: 1986
https://doi.org/10.1016/B978-0-08-033473-8.50049-8
Katz RKatz R(1985)Annotated BibliographyInformation Management for Engineering Design10.1007/978-3-642-82438-8_8(89-93)Online publication date: 1985
https://doi.org/10.1007/978-3-642-82438-8_8
McCormick SLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)EXCLProceedings of the 21st Design Automation Conference10.5555/800033.800863(616-623)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800863
Kawamura MTakagi HHirabayashi KLambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)Functional verification of memory circuits from mask artwork dataProceedings of the 21st Design Automation Conference10.5555/800033.800801(228-234)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800801
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Programs for verifying circuit connectivity of mos/lsi mask artwork

Recognizing VLSI Circuits from Mask Artwork

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Programs for verifying circuit connectivity of mos/lsi mask artwork

Recognizing VLSI Circuits from Mask Artwork

Functional verification of memory circuits from mask artwork data

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