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Functional simulation in the lamp system

Published: 28 June 1976 Publication History

Abstract

The effective use of simulation for logic verification and test evaluation frequently requires simulation capabilities at different levels of detail. This paper discusses the functional level simulation capability in the LAMP system at Bell Laboratories and its relation to gate level simulation. The Function Definition Language (FDL) used for specifying the behavior of functional blocks is discussed. Functions described in this language can be embedded in gate level circuits and simulated to determine the normal circuit behavior or faulty behavior. Classical faults external to functions and user specified internal faults in functions may be simulated. The effectiveness of functional simulation has been demonstrated in a number of applications such as memory modules in a large controller of an Electronic Switching System, the ROM in a small controller and an entire microprocessor treated as an interconnection of a few functional blocks.

References

[1]
F. H. Hardie and R. J. Suhocki, "Design and Use of Fault Simulation for Saturn Computer Design," IEEE Trans. Elec. Comp, EC-16, pp. 412-429, August, 1967.
[2]
T. T. Butler, T. G. Hallin, K. W. Johnson, and J. J. Kulzer, "LAMP: Application to Switching System Development," BSTJ, vol. 53, pp. 1535-1555, October, 1974.
[3]
Proc. 12th Design Automation Conference, June, 1975 (Several papers on State of the Art in Design Automation.)
[4]
G. G. Hays, "Computer Aided Design: Simulation of Digital Design Logic," IEEE Trans. Comp., C-18, pp. 1-10, January, 1969.
[5]
S. A. Szygenda, "TEGAS2 - Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic," Proc. 9th ACM-IEEE Design Automation Workshop, pp. 116-127, June, 1972.
[6]
S. A. Szygenda and A. A. Lekkos, "Integrated Techniques for Functional and Gate Level Digital Logic Simulation," Proc. 10th Design Automation Workshop, pp. 159-172, June, 1973.
[7]
D. B. Armstrong, "A Deductive Method of Simulating Faults in Logic Circuits," IEEE Trans. Comp., C-21, pp. 464-471, May, 1972.
[8]
H. Y. Chang, G. W. Smith, Jr. and R. B. Walford, "LAMP: System Description," BSTJ vol. 53, pp. 1431-1449, October, 1974.
[9]
S. G. Chappell, C. H. Elmendorf and L. D. Schmidt, "LAMP: Logic-Circuit Simulators," BSTJ vol. 53, pp. 1451-1476, October, 1974.
[10]
D. E. Knuth, The Art of Computer Programming, Vol. 1 Fundamental Algorithms, Addison-Wesley, Reading, MA, 1968.
[11]
P. R. Menon, "A Simulation Program for Logic Circuits," Bell Telephone Laboratories Internal Memorandum, March, 1965.
[12]
A. V. Aho, J. E. Hopcroft and J. D. Ullman, The Design and Analysis of Computer Algorithms, Addison-Wesley, Reading, MA, 1974.

Cited By

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  • (1988)SABLE: A tool for generating structured, multi-level simulationsPapers on Twenty-five years of electronic design automation10.1145/62882.62925(365-272)Online publication date: 1-Jun-1988
  • (1981)Computer-aided design of electrical circuits Simulation techniques (A Tutorial)Proceedings of the ACM '81 conference10.1145/800175.809871(199-203)Online publication date: 1-Jan-1981
  • (1980)Functional level simulation at RaytheonProceedings of the 17th Design Automation Conference10.1145/800139.804597(634-641)Online publication date: 23-Jun-1980
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cover image ACM Conferences
DAC '76: Proceedings of the 13th Design Automation Conference
June 1976
512 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 June 1976

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Cited By

View all
  • (1988)SABLE: A tool for generating structured, multi-level simulationsPapers on Twenty-five years of electronic design automation10.1145/62882.62925(365-272)Online publication date: 1-Jun-1988
  • (1981)Computer-aided design of electrical circuits Simulation techniques (A Tutorial)Proceedings of the ACM '81 conference10.1145/800175.809871(199-203)Online publication date: 1-Jan-1981
  • (1980)Functional level simulation at RaytheonProceedings of the 17th Design Automation Conference10.1145/800139.804597(634-641)Online publication date: 23-Jun-1980
  • (1980)MIXSProceedings of the 17th Design Automation Conference10.1145/800139.804596(626-633)Online publication date: 23-Jun-1980
  • (1980)The incorporation of functional level element routines into an existing digital simulation systemProceedings of the 17th Design Automation Conference10.1145/800139.804561(394-401)Online publication date: 23-Jun-1980
  • (1980)An accurate functional level concurrent fault simulatorProceedings of the 17th Design Automation Conference10.1145/800139.804530(210-217)Online publication date: 23-Jun-1980
  • (1980)The design and implementation of fault insertion capabilities for ISPSProceedings of the 17th Design Automation Conference10.1145/800139.804529(197-209)Online publication date: 23-Jun-1980
  • (1979)Developments in computer simulation of gate level physical logicProceedings of the 16th Design Automation Conference10.5555/800292.811774(561-567)Online publication date: 25-Jun-1979
  • (1979)Hierarchical modeling and simulation in VISTAProceedings of the 16th Design Automation Conference10.5555/800292.811747(403-405)Online publication date: 25-Jun-1979
  • (1979)SABLEProceedings of the 16th Design Automation Conference10.5555/800292.811721(272-279)Online publication date: 25-Jun-1979
  • Show More Cited By

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