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Partitioning and ordering of logic equations for optimum MOS LSI device layout

Published: 28 June 1971 Publication History

Abstract

The concepts underlying a versatile tiered layout design scheme for MOS LSI logic devices is presented. A series of three computer-aided design programs is discussed which provide designers with information permitting rapid organization of minimum area layout designs.

References

[1]
R. P. Larsen, "Computer-Aided Preliminary Layout Design of Customized MOS Arrays", IEEE Trans. on Computers, Vol. C-20, No. 5, May 1971.
[2]
A. Weinberger, "Large Scale Integration of MOS Complex Logic; A Layout Method", IEEE Journal on Solid-State Circuits, Vol. SC-2, No. 4, December 1967, pp. 182-190.

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cover image ACM Conferences
DAC '71: Proceedings of the 8th Design Automation Workshop
June 1971
387 pages
ISBN:9781450374651
DOI:10.1145/800158
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 28 June 1971

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