Article

An MTCMOS design methodology and its application to mobile computing

Authors:

Jeong-Taek KongAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 110 - 115

https://doi.org/10.1145/871506.871536

Published: 25 August 2003 Publication History

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Abstract

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

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Cited By

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Ul Haq SSharma V(2024)Energy-Efficient Design for Logic Circuits Using a Leakage Control Configuration in FinFET TechnologyJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01026-x105:4(903-911)Online publication date: 8-Mar-2024
https://doi.org/10.1007/s40031-024-01026-x
Shin YHeo SKim HChoi J(2018)Supply switching with ground collapseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89922815:7(758-766)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.899228
Abdollahi AFallah FPedram M(2018)A robust power gating structure and power mode transition strategy for MTCMOS designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89109315:1(80-89)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.891093
Show More Cited By

Index Terms

An MTCMOS design methodology and its application to mobile computing
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Ul Haq SSharma V(2024)Energy-Efficient Design for Logic Circuits Using a Leakage Control Configuration in FinFET TechnologyJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01026-x105:4(903-911)Online publication date: 8-Mar-2024
https://doi.org/10.1007/s40031-024-01026-x
Shin YHeo SKim HChoi J(2018)Supply switching with ground collapseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89922815:7(758-766)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.899228
Abdollahi AFallah FPedram M(2018)A robust power gating structure and power mode transition strategy for MTCMOS designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89109315:1(80-89)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2007.891093
Kong J(2018)CAD for nanometer silicon design challenges and successIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.83629412:11(1132-1147)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2004.836294
Ghaffarishad HMohammadzadeh NGhaznavi‐Ghoushchi M(2018) A power‐performance tunable logic with adjustable threshold pseudo‐dynamic building blocks and CMOS compatibility International Journal of Circuit Theory and Applications10.1002/cta.244746:4(796-811)Online publication date: 23-Jan-2018
https://doi.org/10.1002/cta.2447
Levi IFish A(2017)Alternative Logic Families for Energy-Efficient and High Performance Chip DesignGreen Photonics and Electronics10.1007/978-3-319-67002-7_6(139-172)Online publication date: 19-Nov-2017
https://doi.org/10.1007/978-3-319-67002-7_6
Greenberg SRabinowicz JManor E(2015)Selective State Retention Power Gating Based on Formal VerificationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2014.237303162:3(807-815)Online publication date: Mar-2015
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Liang ZZhang WMa Y(2014)Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register FilesACM Transactions on Architecture and Code Optimization (TACO)10.1145/263221811:2(1-26)Online publication date: 15-Jul-2014
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Greenberg SRabinowicz JTsechanski RPaperno E(2014)Selective State Retention Power Gating Based on Gate-Level AnalysisIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2013.228602961:4(1095-1104)Online publication date: Apr-2014
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Sudha DRani C(2014)SCPG: A new technique to reduce leakage power in 16-bit binary multiplier2014 IEEE International Conference on Computational Intelligence and Computing Research10.1109/ICCIC.2014.7238529(1-7)Online publication date: Dec-2014
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Design methodology for fine-grained leakage control in MTCMOS

Design & Optimization of FinFET Based Schmitt Trigger Using Leakage Reduction Techniques

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Design methodology for fine-grained leakage control in MTCMOS

Design & Optimization of FinFET Based Schmitt Trigger Using Leakage Reduction Techniques

Low power shift register using MTCMOS edge-trigger D flip flop transmission gate in sub-threshold region

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