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Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

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Kurt KeutzerAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 158 - 163

https://doi.org/10.1145/871506.871545

Published: 25 August 2003 Publication History

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Abstract

We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.

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Cited By

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Mangiras DDimitrakopoulos G(2021)Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage AssignmentTechnologies10.3390/technologies90400929:4(92)Online publication date: 26-Nov-2021
https://doi.org/10.3390/technologies9040092
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Multiple On-Chip Power Supply SystemsOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_40(603-617)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_40
Sharma AChinnery DBhardwaj SChu CMarculescu DLiu F(2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840879
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Index Terms

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Mangiras DDimitrakopoulos G(2021)Incremental Lagrangian Relaxation Based Discrete Gate Sizing and Threshold Voltage AssignmentTechnologies10.3390/technologies90400929:4(92)Online publication date: 26-Nov-2021
https://doi.org/10.3390/technologies9040092
P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)Multiple On-Chip Power Supply SystemsOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_40(603-617)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_40
Sharma AChinnery DBhardwaj SChu CMarculescu DLiu F(2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840879
Xie JChen CJones ALi HCoskun AMargala M(2015)Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay ModelProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742094(361-366)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742094
Rakai LFarshidi A(2015)Sizing Digital Circuits Using Convex Optimization TechniquesComputational Intelligence in Digital and Network Designs and Applications10.1007/978-3-319-20071-2_1(3-32)Online publication date: 15-Jul-2015
https://doi.org/10.1007/978-3-319-20071-2_1
Livramento VGuth CGüntzel JJohann M(2014)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian RelaxationACM Transactions on Design Automation of Electronic Systems10.1145/264795619:4(1-25)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647956
Livramento VGuth CGüntzel JJohann MMacii E(2013)Fast and efficient lagrangian relaxation-based discrete gate sizingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485725(1855-1860)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485725
Mok SLee JGupta P(2013)Discrete sizing for leakage power optimization in physical designACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020618:1(1-11)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390206
Zjajo AZjajo A(2013)Random Process Variation in Deep-Submicron CMOSStochastic Process Variation in Deep-Submicron CMOS10.1007/978-94-007-7781-1_2(17-54)Online publication date: 14-Nov-2013
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Huang HHsieh T(2011)3D area-aware partitioning for floorplannerProceedings of the 5th WSEAS international conference on Circuits, systems and signals10.5555/2028256.2028264(35-38)Online publication date: 14-Jul-2011
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Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

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Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

Design and analysis of two low-power SRAM cell structures

Low-power technology mapping for FPGA architectures with dual supply voltages

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