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Checkpointing alternatives for high performance, power-aware processors

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Andreas MoshovosAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

Pages 318 - 321

https://doi.org/10.1145/871506.871585

Published: 25 August 2003 Publication History

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Abstract

High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes unattractive in terms of resource and power requirements for future generation processors. We propose out-of-order checkpoint release and checkpoint prediction, two alternatives that require significantly less resources and power while maintaining high-performance. We demonstrate their utility at the register alias table (RAT). Our methods reduce the number of RAT checkpoints to 1/3 (from 48 down to 16) for an aggressive, 8-way superscalar processor with a 256-entry instruction window. Using a 0.18um process model we estimate that RAT power is reduced by 24%.

References

[1]

K. C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE MICRO, April, 1996.

Digital Library

Google Scholar

[2]

S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proc. of the 24th Int'l Symposium on Computer Architecture, June 1997.

Digital Library

Google Scholar

[3]

R. P. Colwell and R. L. Steck, A 0.6um BiCMOS Processor with Dynamic Execution, In Proc. International Solid State Circuits Conference, Feb. 1995.

Crossref

Google Scholar

[4]

D. Brooks, V. Tiwari M. Martonosi Wattch: A Framework for Architectural-Level Power Analysis and Optimizations, Proc of the 27th Int'l Symposium on Computer Architecture, 2000.

Digital Library

Google Scholar

[5]

P6 Power Data, Intel Corp.

Google Scholar

[6]

D. Burger and T. Austin, The Simplescalar Simulation Environment, Univ. of Wisconsin-Madison, Computer Sciences Dept. Technical Report.

Google Scholar

[7]

E. Jacobsen, E. Rotenberg, and J. E. Smith. Assigning Confidence to Conditional Branch Predictions. In Proc. Int'l Symposium on Microarchitecture, December 1996.

Digital Library

Google Scholar

[8]

D. Grunwald, A. Klusser, S. Manne and A. Plezkun, Confidence Estimation for Speculation Control, In Proc. of the 25th Int'l Symposium on Computer Architecture, June, 1998.

Digital Library

Google Scholar

[9]

J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 2nd Edition, Morgan Kaufman Publishers.

Digital Library

Google Scholar

Cited By

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Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614272
Irie HKoizumi TFukuda AAkaki SNakae SBessho YShioya RNotsu TYoda KIshihara TSakai SOskin MInoue K(2018)STRAIGHTProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00019(121-133)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00019
SHIOYA RANDO H(2016)Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy EfficiencyIEICE Transactions on Information and Systems10.1587/transinf.2015EDP7270E99.D:3(630-640)Online publication date: 2016
https://doi.org/10.1587/transinf.2015EDP7270
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Index Terms

Checkpointing alternatives for high performance, power-aware processors
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Robustness

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Koizumi TShioya RSugita SAmano TDegawa YKadomoto JIrie HSakai S(2023)Clockhands: Rename-free Instruction Set Architecture for Out-of-order ProcessorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614272(1-16)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614272
Irie HKoizumi TFukuda AAkaki SNakae SBessho YShioya RNotsu TYoda KIshihara TSakai SOskin MInoue K(2018)STRAIGHTProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00019(121-133)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00019
SHIOYA RANDO H(2016)Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy EfficiencyIEICE Transactions on Information and Systems10.1587/transinf.2015EDP7270E99.D:3(630-640)Online publication date: 2016
https://doi.org/10.1587/transinf.2015EDP7270
Eckert YManne SSchulte MWood DShanbhag NPoncino MChou PAmerasekera A(2012)Something old and something newProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333748(385-390)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333748
Choi MPark JLim SJeong Y(2012)Achieving reliable system performance by fast recovery of branch miss predictionJournal of Network and Computer Applications10.1016/j.jnca.2011.03.01535:3(982-991)Online publication date: 1-May-2012
https://dl.acm.org/doi/10.1016/j.jnca.2011.03.015
Latorre FMagklis GGonzález JChaparro PGonzález A(2011)CROBTransactions on high-performance embedded architectures and compilers III10.5555/1980776.1980785(115-134)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.5555/1980776.1980785
Latorre FMagklis GGonzález JChaparro PGonzález A(2011)CROBProceedings of the 2011 conference on Transactions on High-Performance Embedded Architectures and Compilers III - Volume 659010.1007/978-3-642-19448-1_7(115-134)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1007/978-3-642-19448-1_7
Safi EMoshovos AVeneris A(2010)On the latency and energy of checkpointed superscalar register alias tablesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201212818:3(365-377)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2012128
Zeng HYourst MGhose KHenkel JKeshavarzi AChang NGhani T(2009)An energy-efficient checkpointing mechanism for out of order commit processorProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594279(183-188)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594279
Golander AWeiss S(2009)Checkpoint allocation and releaseACM Transactions on Architecture and Code Optimization10.1145/1582710.15827126:3(1-27)Online publication date: 2-Oct-2009
https://dl.acm.org/doi/10.1145/1582710.1582712
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Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors

Power-aware scoreboard alternatives for multimedia processors

Hiding the misprediction penalty of a resource-efficient high-performance processor

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