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Hardware/software tradeoffs for increased performance

Authors:

John Hennessy,

Norman Jouppi,

Forest Baskett,

Thomas Gross, and

John GillAuthors Info & Claims

ACM SIGPLAN Notices, Volume 17, Issue 4

Pages 2 - 11

https://doi.org/10.1145/960120.801820

Published: 01 March 1982 Publication History

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Abstract

Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous tradeoffs across all three areas: hardware, software support, and systems support. Recent trends lean towards extensive hardware support for both the compiler and operating systems software. However, consideration of all possible design tradeoffs may often lead to less hardware support. Several examples of this approach are presented, including: omission of condition codes, word-addressed machines, and imposing pipeline interlocks in software. The specifics and performance of these approaches are examined with respect to the MIPS processor.

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Cited By

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Einarsson BGentleman W(1984)Mixed language programmingSoftware—Practice & Experience10.1002/spe.438014041014:4(383-392)Online publication date: 18-Jun-1984
https://dl.acm.org/doi/10.1002/spe.4380140410
McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
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Index Terms

Hardware/software tradeoffs for increased performance
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. General and reference
  1. Cross-computing tools and techniques
    1. Performance

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Hardware/software tradeoffs for increased performance
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Hardware/software tradeoffs for increased performance

Most new computer architectures are concerned with maximizing performance by providing suitable instruction sets for compiled code and providing support for systems functions. We argue that the most effective design methodology must make simultaneous ...
Read More

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Information

Published In

ACM SIGPLAN Notices Volume 17, Issue 4

Proceedings of the 1982 symposium on Architectural support for programming languages and operating systems

April 1982

209 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/960120

Issue’s Table of Contents

ASPLOS I: Proceedings of the first international symposium on Architectural support for programming languages and operating systems
March 1982
209 pages
ISBN:0897910664
DOI:10.1145/800050
Chairmen:
David R. Ditzel,
Lloyd I. Dickman

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 1982

Published in SIGPLAN Volume 17, Issue 4

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Cited By

View all

Einarsson BGentleman W(1984)Mixed language programmingSoftware—Practice & Experience10.1002/spe.438014041014:4(383-392)Online publication date: 18-Jun-1984
https://dl.acm.org/doi/10.1002/spe.4380140410
McFarlin DZilles C(2015)Branch vanguardACM SIGARCH Computer Architecture News10.1145/2872887.275040043:3S(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750400
McFarlin DZilles CMarr DAlbonesi D(2015)Branch vanguardProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750400(323-335)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750400
Großschädl JPage DTillich S(2012)Efficient java implementation of elliptic curve cryptography for J2ME-Enabled mobile devicesProceedings of the 6th IFIP WG 11.2 international conference on Information Security Theory and Practice: security, privacy and trust in computing systems and ambient intelligent ecosystems10.1007/978-3-642-30955-7_17(189-207)Online publication date: 20-Jun-2012
https://dl.acm.org/doi/10.1007/978-3-642-30955-7_17
Govindarajan R(2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch17
Govindarajan R(2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch19
Magenheimer DChristian T(2004)vBladesProceedings of the 3rd conference on Virtual Machine Research And Technology Symposium - Volume 310.5555/1267242.1267248(6-6)Online publication date: 6-May-2004
https://dl.acm.org/doi/10.5555/1267242.1267248
Sohi GVajapeyam S(1998)Instruction issue logic for high-performance, interruptable pipelined processors25 years of the international symposia on Computer architecture (selected papers)10.1145/285930.285992(329-336)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1145/285930.285992
Smith JPleszkun A(1998)Implementation of precise interrupts in pipelined processors25 years of the international symposia on Computer architecture (selected papers)10.1145/285930.285988(291-299)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1145/285930.285988
Richardson WBrunvand E(1996)FredProceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems10.5555/785164.785210Online publication date: 18-Mar-1996
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Abstract

References

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Comparing software and hardware schemes for reducing the cost of branches