An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs

Efficient management of the logic resource available is one of the biggest problems faced by the embedded systems based on FPGA, in which their functionality can be partially modified at run-time without stopping the operation of the whole system. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. Dynamical reconfiguration can be necessary to relocate a running physical configuration, and to rearrange the logic resources into the variety of physical portions. Our proposed algorithm is formally developed to enable implementing an on-line management of FPGA logic resources, supporting the rearrangement of running functions, releasing enough contiguous space for configuration of new incoming functions, and performing the defragmentation in a way completely transparent to the applications currently running. Therefore, on-line scheduling of tasks in the spatial and temporal domains becomes possible, enabling the implementation of virtual hardware concept.