Article

Early-stage power grid analysis for uncertain working modes

Authors:

Haifeng Qian,

Sani R. Nassif,

Sachin S. SapatnekarAuthors Info & Claims

ISPD '04: Proceedings of the 2004 international symposium on Physical design

Pages 132 - 137

https://doi.org/10.1145/981066.981095

Published: 18 April 2004 Publication History

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Abstract

High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact ILP method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43K nodes is analyzed within 70 seconds, and the worst-case scenarios found correlate well with the results from an ILP solver.

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Cited By

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Xiong XWang J(2011)Dual Algorithms for Vectorless Power Grid Verification Under Linear Current ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215843330:10(1469-1482)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2158433
Xiong XWang JSapatnekar S(2010)An efficient dual algorithm for vectorless power grid verification under linear current constraintsProceedings of the 47th Design Automation Conference10.1145/1837274.1837484(837-842)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837484
Karampatzakis DTsiampas MEvmorfopoulos NStamoulis G(2008)A Design Flow for the Precise Identification of the Worst-Case Voltage Drop in Power Grid AnalysesProceedings of the 2008 Panhellenic Conference on Informatics10.1109/PCI.2008.25(135-139)Online publication date: 28-Aug-2008
https://dl.acm.org/doi/10.1109/PCI.2008.25
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Index Terms

Early-stage power grid analysis for uncertain working modes
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

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Published In

ISPD '04: Proceedings of the 2004 international symposium on Physical design

April 2004

226 pages

ISBN:1581138172

DOI:10.1145/981066

General Chair:
Charles J. Alpert,
IBM
,
Program Chair:
Patrick Groeneveld
Eindhoven University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 April 2004

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ISPD04: International Symposium on Physical Design 2004

April 18 - 21, 2004

Arizona, Phoenix, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

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Xiong XWang J(2011)Dual Algorithms for Vectorless Power Grid Verification Under Linear Current ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.215843330:10(1469-1482)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1109/TCAD.2011.2158433
Xiong XWang JSapatnekar S(2010)An efficient dual algorithm for vectorless power grid verification under linear current constraintsProceedings of the 47th Design Automation Conference10.1145/1837274.1837484(837-842)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837484
Karampatzakis DTsiampas MEvmorfopoulos NStamoulis G(2008)A Design Flow for the Precise Identification of the Worst-Case Voltage Drop in Power Grid AnalysesProceedings of the 2008 Panhellenic Conference on Informatics10.1109/PCI.2008.25(135-139)Online publication date: 28-Aug-2008
https://dl.acm.org/doi/10.1109/PCI.2008.25
Evmorfopoulos NKarampatzakis DStamoulis GHassoun S(2006)Precise identification of the worst-case voltage drop conditions in power grid verificationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233526(112-118)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233526
Evmorfopoulos NKarampatzakis DStamoulis G(2006)Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320074(112-118)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320074
Pant SBlaauw D(2005)Static timing analysis considering power supply variationsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129655(365-371)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129655
Kouroussis DFerzli INajm F(2005)Incremental partitioning-based vectorless power grid verificationProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129654(358-364)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129654
Leung K(2005)SPIDERProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129609(33-38)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129609
Pant SBlaauw D(2005)Static timing analysis considering power supply variationsICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560095(365-372)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560095
Kouroussis DFerzli INajm F(2005)Incremental partitioning-based vectorless power grid verificationICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560094(358-364)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560094

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