Article

Innovate or perish: FPGA physical design

Authors:

Taraneh Taghavi,

Abhishek Ranjan,

Majid SarrafzadehAuthors Info & Claims

ISPD '04: Proceedings of the 2004 international symposium on Physical design

Pages 148 - 155

https://doi.org/10.1145/981066.981099

Published: 18 April 2004 Publication History

Abstract

The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. The size and complexity of modern FPGAs has far outpaced the innovations in FPGA physical design. The problems faced by FPGA designers are similar in nature to those that preoccupy ASIC designers, namely, interconnect delays and design management. However, this paper will show that a simple re-targeting of ASIC physical design methodologies and algorithms to the FPGA domain will not suffice. We will show that several well researched problems in the ASIC world need new problem formulations and algorithms research to be useful for today's FPGAs. Partitioning, floorplanning, placement, delay estimation schemes are only some of the topics that need complete overhaul. We will give problem formulations, motivated by experimental results, for some of these topics as applicable in the FPGA domain.

References

[1]

A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-based Placement," ISPD, pp. 4--11, 1998.

Digital Library

[2]

A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?" in Design Automation Conference, pp. 477--482, 2000.

Digital Library

[3]

C. Chen and C. Tsui, "Timing Optimization of Logic Network using Gate Duplication", ASP-DAC, pp. 233--236, 1999.

[4]

C. S. Chen, Y.-W. Tsay, T. HwangA. C. H. Wu and Y.-L. Lin, "Combining Technology Mapping and Placement for Delay-Optimization in FPGA Designs," ICCAD, pp. 240--247, 1993.

Digital Library

[5]

J. Cong and Y. Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," ICCAD, pp. 48--53, 1992.

Digital Library

[6]

W. E. Donath, "Placement and average interconnection lengths of computer logic", IEEE Transactions on Circuits and Systems, CAS-26(4):272--277, April 1979.

[7]

W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wide Band Amplifiers," J. Applied Physics, 19(1), 1948.

[8]

J. M. Emmert, and D. Bhatia, "A Methodology for Fast FPGA Floorplanning", Proc. FPGA, 1999.

Digital Library

[9]

P. N. Guo, C.-K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non-Slicing Floorplan and Its Applications", Proc. DAC, pp. 268--273, 1999.

Digital Library

[10]

M. Z. Kang and W. Dai., "Arbitrary Rectilinear Block Packing Based on Sequence Pair", Proc. ICCAD, pp. 259--266, 1998.

Digital Library

[11]

T. Karnik, "Hierarchical Timing-Driven Partitioning and Placement for Symmetrical FPGAs," PhD thesis, University of Illinois at Urbana-Champaign, 1995.

Digital Library

[12]

T. Karnik and S. M. Kang, "An Empirical Model For Accurate Estimation of Routing Delay in FPGAs," ICCAD, pp. 328--331, 1995.

Digital Library

[13]

G. Karypis and V. Kumar, "Multilevel k-way Hyper-graph Partitioning", in Design Automation Conference, pp. 343--348, 1999.

Digital Library

[14]

J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", IEEE Transactions on Computer Aided Design, 10(3): 365--370, 1991.

Digital Library

[15]

H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "VLSI Module Placement Based on Rectangle-Packing by the Sequence Pair", IEEE Trans. On CAD, vol 15(12), pp. 1518--1524, 1996.

Digital Library

[16]

R. Nair, C. L. Berman, P. Hauge, E. Yoffa, "Generation of Performance Constraints for Layout", IEEE Trans. On CAD, vol. 8(8), pp. 860--874, 1989.

Digital Library

[17]

R. H. J. M. Otten, "Efficient Floorplan Optimization", ICCD, pp. 499--503, IEEE/ACM, 1983.

[18]

R. H. J. M. Otten, "Automatic Floorplan Design", Proc. DAC, pp.261--267, 1992.

Digital Library

[19]

L. Stockmeyer, "Optimal Orientation of Cells in Slicing Floorplan Designs", Information and Control,57(2), pp. 91--101, 1983.

Digital Library

[20]

X. Tang, R. Tian and D. F. Wong, "Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation", DATE 2000, pp. 106--111.

Digital Library

[21]

X. Tang and D. F. Wong, "FAST-SP: A Fast Algorithm for Block Placement Based on Sequence Pair", ASPDAC 2001.

Digital Library

[22]

A. Ranjan, K. Bazargan, M. Sarrafzadeh, "Fast Hierarchical Floorplanning with Congestion and Timing Control", IEEE International Conference on Computer Design (ICCD), pp. 357--362, September 2000.

Digital Library

[23]

J. Vygen, "Algorithms For Large-scale Flat Placement", Proc. Design Automation Conference, pp. 746--51, 1997.

Digital Library

[24]

M. Wang, X. Yang and M. Sarrafzadeh, "Dragon2000: Standard-Cell Placement Tool For Large Industry Circuits", ICCAD, pp. 160--163, 2000.

Digital Library

[25]

Xilinx Inc., http://www.xilinx.com/

[26]

N. Selvakkumaran, A. Ranjan, S. Raje, G. Karypis, "Partitioning Algorithms for FPGAs with Heterogenous Resources", Symposium on Field Programmable Gate Arrays, 2004.

Digital Library

[27]

M. Wang, A. Ranjan, S. Raje, "Multi-Million Gate FPGA Physical Design Challenges", ICCAD, pp. 891--898, 2004.

Digital Library

Cited By

Gregerson AChadha AMorrow K(2013)Multi-personality partitioning for heterogeneous systems2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718375(314-317)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718375
Silva MFerreira J(2012)Run-time generation of partial FPGA configurationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2011.10.00158:1(24-37)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1016/j.sysarc.2011.10.001
Gopalakrishnan PLi XPileggi LSentovich E(2006)Architecture-aware FPGA placement using metric embeddingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147033(460-465)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147033
Show More Cited By

Index Terms

Innovate or perish: FPGA physical design
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
    1. Application-specific VLSI designs

Recommendations

Physical design for FPGAs
ISPD '01: Proceedings of the 2001 international symposium on Physical design

FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. In this paper we discuss the state-of-the-art in FPGA ...
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs

In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and ...
Routing-architecture-aware analytical placement for heterogeneous FPGAs
DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Placement is a crucial stage for FPGA implementation. Most FPGA placers optimize their placement results by minimizing half-perimeter wirelength (HPWL). Due to the segmented routing architecture in FPGAs, however, the HPWL function cannot model routed ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISPD '04: Proceedings of the 2004 international symposium on Physical design

April 2004

226 pages

ISBN:1581138172

DOI:10.1145/981066

General Chair:
Charles J. Alpert,
IBM
,
Program Chair:
Patrick Groeneveld
Eindhoven University

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 April 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISPD04

Sponsor:

ISPD04: International Symposium on Physical Design 2004

April 18 - 21, 2004

Arizona, Phoenix, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
849
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Gregerson AChadha AMorrow K(2013)Multi-personality partitioning for heterogeneous systems2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718375(314-317)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718375
Silva MFerreira J(2012)Run-time generation of partial FPGA configurationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2011.10.00158:1(24-37)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1016/j.sysarc.2011.10.001
Gopalakrishnan PLi XPileggi LSentovich E(2006)Architecture-aware FPGA placement using metric embeddingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147033(460-465)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1147033
Da Silva MFerreira RGarcia ACardoso J(2006)Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)10.1109/RECONF.2006.307749(1-10)Online publication date: Sep-2006
https://doi.org/10.1109/RECONF.2006.307749
Veredas FScheppler MZhai BPfleiderer H(2006)Regular Routing Architecture for a LUT-based MPGAProceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures10.1109/ISVLSI.2006.78Online publication date: 2-Mar-2006
https://dl.acm.org/doi/10.1109/ISVLSI.2006.78
Yuan JDong SHong XWu YTang T(2005)LFF algorithm for heterogeneous FPGA floorplanningProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120839(1123-1126)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120839
Rautela DKatti R(2005)Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing ResourcesProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.26(232-237)Online publication date: 11-May-2005
https://dl.acm.org/doi/10.1109/ISVLSI.2005.26
Jun Yuan Sheqin Dong Xianlong Hong Yuliang Wu (2005)LFF algorithm for heterogeneous FPGA floorplanningProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466538(1123-1126)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466538

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents