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DSPs: Back to the Future: To understand where DSPs are headed, we must look at where they’ve come from.

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W. Patrick HaysAuthors Info & Claims

Queue, Volume 2, Issue 1

Pages 42 - 51

https://doi.org/10.1145/984458.984485

Published: 01 March 2004 Publication History

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Abstract

From the dawn of the DSP (digital signal processor), an old quote still echoes: "Oh, no! We’ll have to use state-of-the-art 5µm NMOS!" The speaker’s name is lost in the fog of history, as are many things from the ancient days of 5µm chip design. This quote refers to the first Bell Labs DSP whose mask set in fact underwent a 10 percent linear lithographic shrink to 4.5µm NMOS (N-channel metal oxide semiconductor) channel length and taped out in late 1979 with an aggressive full-custom circuit design. The designer I quoted had realized that the best technology of the time would be required to meet the performance demands of the then cutting-edge digital Touch-Tone receiver.

References

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1. ISSCC Digest of Technical Papers XXII, February 1979.

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2. ISSCC Digest of Technical Papers XXIII, February 1980.

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3. Strauss, W. Forward Concepts. Quote supplied for this article.

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4. Tredennick, N. The death of the DSP. June 6, 2000; see: http://www.ttivanguard.com/dublin/dspdealth.pdf.

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5. Input samples are memory based rather than from I/O registers because they are reused cyclically.

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6. Howard Aiken, a WWII computer pioneer, classified processors according to the number of buses used. According to this classification, DSPs aren't "modified" Harvard architectures. They are, in fact, "Class III" Aiken machines.

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7. How do you pack over 130 instructions into 16 bits? With numerous special registers.

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8. The next-generation 'C64xx restored multiply-accumulates.

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9. Speech recognition isn't included in the tally of the worst-case load because it's an offline function.

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10. Probell, J. Improving application performance with instruction set extensions to embedded processors. DesignCon 2004; see: http://www.ultradatacorp.com/ publications.html.

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11. Yoshida, J. TI and UB Video get a jump on H.264 decoding. EE Times (December 2, 2002); http: //www.eetimes.com/semi/news/OEG20021202S0048.

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12. Hennessy, J. L., and Patterson, D. Computer Architecture: A Quantitative Approach, Appendix C. Morgan Kaufman, San Francisco: CA, 1996.

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13. See reference 4.

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Ignatov ATimofte RChou WWang KWu MHartley TVan Gool L(2018)AI Benchmark: Running Deep Neural Networks on Android SmartphonesComputer Vision – ECCV 2018 Workshops10.1007/978-3-030-11021-5_19(288-314)Online publication date: 8-Sep-2018
https://dl.acm.org/doi/10.1007/978-3-030-11021-5_19

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DSPs: Back to the Future: To understand where DSPs are headed, we must look at where they’ve come from.

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Published In

Queue Volume 2, Issue 1

DSPs

March 2004

84 pages

ISSN:1542-7730

EISSN:1542-7749

DOI:10.1145/984458

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Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 March 2004

Published in QUEUE Volume 2, Issue 1

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Ignatov ATimofte RChou WWang KWu MHartley TVan Gool L(2018)AI Benchmark: Running Deep Neural Networks on Android SmartphonesComputer Vision – ECCV 2018 Workshops10.1007/978-3-030-11021-5_19(288-314)Online publication date: 8-Sep-2018
https://dl.acm.org/doi/10.1007/978-3-030-11021-5_19

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A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology

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