Article

On test generation for transition faults with minimized peak power dissipation

Authors:

Sudhakar M. Reddy,

Irith PomeranzAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 504 - 509

https://doi.org/10.1145/996566.996706

Published: 07 June 2004 Publication History

Abstract

This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests for stuck-at faults. The proposed method is suitable for use in testing scan designs that employ enhanced scan. The method reduces the peak power consumption in benchmark circuits by 19% on the average with essentially the same test set size and the same fault coverage compared to an earlier method.

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Cited By

Pomeranz I(2020)Switching Activity of Faulty Circuits in Presence of Multiple Transition FaultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290232639:4(936-945)Online publication date: Apr-2020
https://doi.org/10.1109/TCAD.2019.2902326
Pomeranz I(2018)Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2018.8602967(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/DFT.2018.8602967
Pomeranz IReddy S(2016)On the Switching Activity in Faulty Circuits During Test Application2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.12(13-18)Online publication date: Nov-2016
https://doi.org/10.1109/ATS.2016.12
Show More Cited By

Index Terms

On test generation for transition faults with minimized peak power dissipation
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2004

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Cited By

Pomeranz I(2020)Switching Activity of Faulty Circuits in Presence of Multiple Transition FaultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290232639:4(936-945)Online publication date: Apr-2020
https://doi.org/10.1109/TCAD.2019.2902326
Pomeranz I(2018)Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2018.8602967(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/DFT.2018.8602967
Pomeranz IReddy S(2016)On the Switching Activity in Faulty Circuits During Test Application2016 IEEE 25th Asian Test Symposium (ATS)10.1109/ATS.2016.12(13-18)Online publication date: Nov-2016
https://doi.org/10.1109/ATS.2016.12
Pomeranz I(2014)Low-power skewed-load tests based on functional broadside testsACM Transactions on Design Automation of Electronic Systems10.1145/256666419:2(1-18)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2566664
Pomeranz I(2014)Low-Power Test Generation by Merging of Functional Broadside Test CubesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.227503722:7(1570-1582)Online publication date: Jul-2014
https://doi.org/10.1109/TVLSI.2013.2275037
Pomeranz I(2013)Low-power test sets under test-related primary input constraintsInternational Journal of Critical Computer-Based Systems10.1504/IJCCBS.2013.0583964:3(265-279)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1504/IJCCBS.2013.058396
Pomeranz I(2013)Functional Broadside Templates for Low-Power Test GenerationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.222851021:12(2321-2325)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2228510
Pomeranz I(2013)Signal-Transition Patterns of Functional Broadside TestsIEEE Transactions on Computers10.1109/TC.2012.14162:12(2544-2549)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1109/TC.2012.141
Pomeranz I(2013)An Adjacent Switching Activity Metric under Functional Broadside TestsIEEE Transactions on Computers10.1109/TC.2011.22462:2(404-410)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TC.2011.224
Lee L(2013)Observation-Oriented ATPG and Scan Chain Disabling for Capture Power ReductionJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5404-x29:5(625-634)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1007/s10836-013-5404-x
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