Article

A new state assignment technique for testing and low power

Authors:

Sungju Park,

Sangwook Cho,

Seiyang Yang,

Maciej CiesielskiAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 510 - 513

https://doi.org/10.1145/996566.996707

Published: 07 June 2004 Publication History

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Abstract

In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feedback cycles are reduced with minimal switching activity on the state variables. Experiment shows significant improvement in power dissipation and testabilities for benchmark circuits.

References

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K. T. Cheng, and V. D. Agrawal, "Design of Sequential Machines for Efficient Test Generation", in Proc. of ICCAD, pp. 358--361, 1989.

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Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1978.

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E. Olson, S.M. Kang, "Low-Power State Assignment for Finite State Machines", proc. IEEE Intl. Workshop on Low Power Design, pp. 63--68, April 1995.

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L.Benini and G. De. Micheli, "State assignment for low power dissipation", IEEE Journal of Solid-State Circuits, vol. 30. March 1995.

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Barkalov ATitarenko LBieganowski JKrzywicki K(2024)Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A ReviewApplied Sciences10.3390/app1407269314:7(2693)Online publication date: 22-Mar-2024
https://doi.org/10.3390/app14072693
Barkalov ATitarenko LMielcarek KMazurkiewicz M(2024)Hardware Reduction for FSMs With Extended State CodesIEEE Access10.1109/ACCESS.2024.337647212(42369-42384)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3376472
Barkalov ATitarenko LMielcarek KMazurkiewicz MKawecka EBarkalov ATitarenko LMielcarek KMazurkiewicz MKawecka E(2022)VLSI-based Logic SynthesisLogic Synthesis for VLSI-Based Combined Finite State Machines10.1007/978-3-031-16027-1_2(33-76)Online publication date: 25-Nov-2022
https://doi.org/10.1007/978-3-031-16027-1_2
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Index Terms

A new state assignment technique for testing and low power
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Hardware test
  2. Robustness

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Information & Contributors

Information

Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Barkalov ATitarenko LBieganowski JKrzywicki K(2024)Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A ReviewApplied Sciences10.3390/app1407269314:7(2693)Online publication date: 22-Mar-2024
https://doi.org/10.3390/app14072693
Barkalov ATitarenko LMielcarek KMazurkiewicz M(2024)Hardware Reduction for FSMs With Extended State CodesIEEE Access10.1109/ACCESS.2024.337647212(42369-42384)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3376472
Barkalov ATitarenko LMielcarek KMazurkiewicz MKawecka EBarkalov ATitarenko LMielcarek KMazurkiewicz MKawecka E(2022)VLSI-based Logic SynthesisLogic Synthesis for VLSI-Based Combined Finite State Machines10.1007/978-3-031-16027-1_2(33-76)Online publication date: 25-Nov-2022
https://doi.org/10.1007/978-3-031-16027-1_2
Barkalov ATitarenko LKrzywicki KSaburova S(2020)Improving the Characteristics of Multi-Level LUT-Based Mealy FSMsElectronics10.3390/electronics91118599:11(1859)Online publication date: 5-Nov-2020
https://doi.org/10.3390/electronics9111859
Barkalov ATitarenko LMielcarek KChmielewski SBarkalov ATitarenko LMielcarek KChmielewski S(2020)Combining Twofold State Assignment with Transformation of Object CodesLogic Synthesis for FPGA-Based Control Units10.1007/978-3-030-38295-7_5(117-149)Online publication date: 9-Jan-2020
https://doi.org/10.1007/978-3-030-38295-7_5
Barkalov ATitarenko LMielcarek KChmielewski SBarkalov ATitarenko LMielcarek KChmielewski S(2020)Twofold State Assignment for Moore FSMsLogic Synthesis for FPGA-Based Control Units10.1007/978-3-030-38295-7_4(91-116)Online publication date: 9-Jan-2020
https://doi.org/10.1007/978-3-030-38295-7_4
Chaudhury SSistla KChattopadhyay S(2018)Genetic algorithm-based FSM synthesis with area-power trade-offsIntegration, the VLSI Journal10.1016/j.vlsi.2008.11.00542:3(376-384)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.vlsi.2008.11.005
Barkalov ATitarenko LBieganowski JBarkalov ATitarenko LBieganowski J(2017)Finite State Machines and Field-Programmable Gate ArraysLogic Synthesis for Finite State Machines Based on Linear Chains of States10.1007/978-3-319-59837-6_2(7-34)Online publication date: 25-Jun-2017
https://doi.org/10.1007/978-3-319-59837-6_2
Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Pradhan SChoudhury P(2015)Low power and high testable Finite State Machine synthesis2015 International Conference and Workshop on Computing and Communication (IEMCON)10.1109/IEMCON.2015.7344528(1-5)Online publication date: Oct-2015
https://doi.org/10.1109/IEMCON.2015.7344528
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