Article

A SAT-based algorithm for reparameterization in symbolic simulation

Authors:

Pankaj Chauhan,

Edmund M. Clarke,

Daniel KroeningAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 524 - 529

https://doi.org/10.1145/996566.996711

Published: 07 June 2004 Publication History

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Abstract

Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one parametric representation to another smaller representation, in a process called reparameterization. For large circuits, the reparametrization step often results in a blowup of BDDs and is expensive due to a large number of quantifications of input variables involved. Efficient SAT solvers have been applied successfully for many verification problems. This paper presents a novel SAT-based reparameterization algorithm that is largely immune to the large number of input variables that need to be quantified. We show experimental results on large industrial circuits and compare our new algorithm to both SAT-based Bounded Model Checking and BDD based symbolic simulation. We were able to achieve on average 3x improvement in time and space over BMC and able to complete many examples that BDD based approach could not even finish.

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Hegde SSethumurugan SCherupalli HDuwe HSartori J(2021)Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded SystemsProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431157(318-324)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431157
Qin YShen SWu QDai HJia Y(2015)Complementary Synthesis for Encoder with Flow Control MechanismACM Transactions on Design Automation of Electronic Systems10.1145/279407921:1(1-26)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2794079
Brauer JKing AKriener J(2011)Existential quantification as incremental SATProceedings of the 23rd international conference on Computer aided verification10.5555/2032305.2032322(191-207)Online publication date: 14-Jul-2011
https://dl.acm.org/doi/10.5555/2032305.2032322
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Index Terms

A SAT-based algorithm for reparameterization in symbolic simulation
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Information & Contributors

Information

Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Hegde SSethumurugan SCherupalli HDuwe HSartori J(2021)Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded SystemsProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431157(318-324)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431157
Qin YShen SWu QDai HJia Y(2015)Complementary Synthesis for Encoder with Flow Control MechanismACM Transactions on Design Automation of Electronic Systems10.1145/279407921:1(1-26)Online publication date: 2-Dec-2015
https://dl.acm.org/doi/10.1145/2794079
Brauer JKing AKriener J(2011)Existential quantification as incremental SATProceedings of the 23rd international conference on Computer aided verification10.5555/2032305.2032322(191-207)Online publication date: 14-Jul-2011
https://dl.acm.org/doi/10.5555/2032305.2032322
Brauer JKing AKriener J(2011)Existential Quantification as Incremental SATComputer Aided Verification10.1007/978-3-642-22110-1_17(191-207)Online publication date: 2011
https://doi.org/10.1007/978-3-642-22110-1_17
Shen SZhang JQin YLi SRoychowdhury J(2009)Synthesizing complementary circuits automaticallyProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687472(381-388)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687472
Claessen KEen NSheeran MSörensson NVoronov AÅkesson K(2009)SAT-Solving in Practice, with a Tutorial Example from Supervisory ControlDiscrete Event Dynamic Systems10.1007/s10626-009-0081-819:4(495-524)Online publication date: 1-Dec-2009
https://dl.acm.org/doi/10.1007/s10626-009-0081-8
Baumgartner JMony H(2005)Maximal input reduction of sequential netlists via synergistic reparameterization and localization strategiesProceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods10.1007/11560548_18(222-237)Online publication date: 3-Oct-2005
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Paruthi VJacobi CWeber K(2005)Efficient symbolic simulation via dynamic scheduling, don't caring, and case splittingProceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods10.1007/11560548_11(114-128)Online publication date: 3-Oct-2005
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Cook BKroening DSharygina N(2005)Symbolic model checking for asynchronous boolean programsProceedings of the 12th international conference on Model Checking Software10.1007/11537328_9(75-90)Online publication date: 22-Aug-2005
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