Pak Chan, Martine Schlag, and Jason Zien. On routability prediction for field programmable gate arrays. In Proceedings of the 1993 Design Automation Conference., pages 326-330, 1993.

Digital Library

Google Scholar

[3]

Wilm E. Donath. Placement and average interconnection lengths of computer logic. IEEE Transactions on Circuits and Systems, CA$-26(4), April 1979.

Crossref

Google Scholar

[4]

Michael Feuer. Connectivity of random logic. IEEE Transactions on Computers, C- 31(1):29-33, January 1982.

Digital Library

Google Scholar

[5]

A. E1 Gamal. Two-dimensional stochastic model for interconnections of master slice integrated circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, CAS-28(2):127- 138, February 1981.

Google Scholar

[6]

J.L. Kouloheris and A. E1 Gamal. Fpga area versus cell granularity- lookup tables and pla cells. In FPGA '92, pages 9-14, 1992.

Google Scholar

[7]

Johnathan Rose, Robert J. Francis, David Lewis, and Paul Chow. Architecture of fieldprogrammable gate arrays: the effect of logic block functionality on area efficiency. IEEE Journal of Solid State Circuits, 25(5):1217- 1225, October 1990.

Crossref

Google Scholar

[8]

Martine Schlag, Pak Chan, and Jackson Kong. Empirical evaluation of multilevel logic minimization tools for a lookup-tablebased field-programmable gate array technology. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 12(5):713-22, may 1993.

Digital Library

Google Scholar

[9]

Martine Schalg, Jackson Kong, and Pak Chan. Routability-driven technology mapping for lookup table-based fpgas. IEEE Transactions on CAD, 13(1):13-26, January 1994.

Digital Library

Google Scholar

[10]

Y.C. Wet and C.K. Cheng. Ratio cut partitioning for hierarchical designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(7), July 1991.

Google Scholar

Cited By

View all

Tziantzioulis GChang TBalkind JTu JGao FWentzlaff D(2022)OPDB: A Scalable and Modular Design BenchmarkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309679441:6(1878-1887)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3096794
Li BLin R(2022)Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937638(3239-3243)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937638
Kahng AKahng ALee HLi J(2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
https://doi.org/10.1109/TCAD.2017.2750072
Show More Cited By

Index Terms

A method for generating random circuits and its application to routability measurement
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Routing and network design problems

Recommendations

Fast and precise routability analysis with conditional design rules
SLIP '18: Proceedings of the 20th System Level Interconnect Prediction Workshop

As pin accessibility encounters more challenges due to the less number of tracks, higher pin density, and more complex design rules, routability has become one bottleneck of sub-10nm designs. Thus, we need a new design methodology for fast turnaround in ...
A fast routability-driven router for FPGAs
FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute power of the available computers. Second, there exists a subset of users who ...
Machine Learning for Electronic Design Automation: A Survey
With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the ...

Comments

Information & Contributors

Information

Published In

FPGA '96: Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

February 1996

158 pages

ISBN:0897917731

DOI:10.1145/228370

Chairmen:
Jonathan Rose
Univ. of Toronto, Toronto, Ont., Canada
,
Carl Ebeling
Univ. of Washington, Seattle

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 1996

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

FPGA96

Sponsor:

SIGDA

FPGA96: 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 11 - 13, 1996

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

35
Total Citations
View Citations
376
Total Downloads

Downloads (Last 12 months)42
Downloads (Last 6 weeks)7

Reflects downloads up to 29 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tziantzioulis GChang TBalkind JTu JGao FWentzlaff D(2022)OPDB: A Scalable and Modular Design BenchmarkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309679441:6(1878-1887)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3096794
Li BLin R(2022)Scalable Synthetic Circuit Generation using Geometry Embedding for CAD Tool Assessment2022 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS48785.2022.9937638(3239-3243)Online publication date: 28-May-2022
https://doi.org/10.1109/ISCAS48785.2022.9937638
Kahng AKahng ALee HLi J(2018)PROBE: A Placement, Routing, Back-End-of-Line Measurement UtilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275007237:7(1459-1472)Online publication date: Jul-2018
https://doi.org/10.1109/TCAD.2017.2750072
Talukdar P(2015)BONY: An algorithm to generate large synthetic combinational benchmark circuits2015 19th International Symposium on VLSI Design and Test10.1109/ISVDAT.2015.7208094(1-2)Online publication date: Jun-2015
https://doi.org/10.1109/ISVDAT.2015.7208094
Srivani LKrishna Giri NGanesh SKamakoti V(2015)Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimizationApplied Soft Computing10.1016/j.asoc.2014.11.00227:C(179-190)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1016/j.asoc.2014.11.002
Kahng ALee HLi JCavallaro JZhang TJones ALi H(2014)Horizontal benchmark extension for improved assessment of physical CAD researchProceedings of the 24th edition of the great lakes symposium on VLSI10.1145/2591513.2591540(27-32)Online publication date: 20-May-2014
https://dl.acm.org/doi/10.1145/2591513.2591540
Kahng AKang SHu JKoh C(2012)Construction of realistic gate sizing benchmarks with known optimal solutionsProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160949(153-160)Online publication date: 25-Mar-2012
https://dl.acm.org/doi/10.1145/2160916.2160949
Whitney MIsailovic NPatel YKubiatowicz J(2009)A fault tolerant, area efficient architecture for Shor's factoring algorithmACM SIGARCH Computer Architecture News10.1145/1555815.155580237:3(383-394)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555815.1555802
Whitney MIsailovic NPatel YKubiatowicz JKeckler SBarroso L(2009)A fault tolerant, area efficient architecture for Shor's factoring algorithmProceedings of the 36th annual international symposium on Computer architecture10.1145/1555754.1555802(383-394)Online publication date: 20-Jun-2009
https://dl.acm.org/doi/10.1145/1555754.1555802
Andrade FSilva LFernandes ALubaszewski MRenovell MGupta R(2008)BenCGenProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404418(164-169)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1145/1404371.1404418
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Fast and precise routability analysis with conditional design rules

A fast routability-driven router for FPGAs

Machine Learning for Electronic Design Automation: A Survey