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On routability prediction for field-programmable gate arrays

Authors:

Pak K. Chan,

Martine D. F. Schlag,

Jason Y. ZienAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 326 - 330

https://doi.org/10.1145/157485.164915

Published: 01 July 1993 Publication History

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Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Al-Hyari ASzentimrey HShamli AMartin TGréwal GAreibi S(2021)A Deep Learning Framework to Predict Routability for FPGA Circuit PlacementACM Transactions on Reconfigurable Technology and Systems10.1145/346537314:3(1-28)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3465373
Chochaev RZheleznikov DIvanova GGavrilov SEnns V(2021)FPGA Routing Architecture Estimation Models and MethodsRussian Microelectronics10.1134/S106373972107004050:7(509-515)Online publication date: 29-Dec-2021
https://doi.org/10.1134/S1063739721070040
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On routability prediction for field-programmable gate arrays
1. Hardware

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In-system-programmable, SRAM-based Field Programmable Gate Arrays (FPGAs) can be used to create processors and coprocessors whose internal architecture as well as interconnections can be reconfigured to match the needs of a given application. Exploiting ...
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DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

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Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Al-Hyari ASzentimrey HShamli AMartin TGréwal GAreibi S(2021)A Deep Learning Framework to Predict Routability for FPGA Circuit PlacementACM Transactions on Reconfigurable Technology and Systems10.1145/346537314:3(1-28)Online publication date: 12-Aug-2021
https://dl.acm.org/doi/10.1145/3465373
Chochaev RZheleznikov DIvanova GGavrilov SEnns V(2021)FPGA Routing Architecture Estimation Models and MethodsRussian Microelectronics10.1134/S106373972107004050:7(509-515)Online publication date: 29-Dec-2021
https://doi.org/10.1134/S1063739721070040
Martin TAreibi SGrewal G(2021)Effective Machine-Learning Models for Predicting Routability During FPGA Placement2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD52597.2021.9531243(1-6)Online publication date: 30-Aug-2021
https://doi.org/10.1109/MLCAD52597.2021.9531243
Al-Hyari AAbuowaimer ZMartin TGréwal GAreibi SVannelli A(2019)Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/333793012:3(1-25)Online publication date: 13-Aug-2019
https://dl.acm.org/doi/10.1145/3337930
Boland DCheng CKahng ALeong P(2017)Reconfigurable ComputingWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7603.pub3(1-17)Online publication date: 15-Feb-2017
https://doi.org/10.1002/047134608X.W7603.pub3
Fang WRose JHutton MChow P(2008)Modeling routing demand for early-stage FPGA architecture developmentProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344694(139-148)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344694
Kannan PBhatia D(2006)Interconnect estimation for FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85731225:8(1523-1534)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.857312
Nam GSakallah KRutenbar R(2006)A new FPGA detailed routing approach via search-based Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.100431121:6(674-684)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2002.1004311
Fernando JJean J(2006)Processor array design with FPGA area constraintIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.74815618:3(253-264)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.748156
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Embedded Design Using Programmable Gate Arrays

Reconfigurable Processing With Field Programmable Gate Arrays

Introduction to Embedded System Design Using Field Programmable Gate Arrays

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Embedded Design Using Programmable Gate Arrays

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Introduction to Embedded System Design Using Field Programmable Gate Arrays

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