research-article

A Deep Learning Framework to Predict Routability for FPGA Circuit Placement

Authors:

Abeer Al-Hyari,

Hannah Szentimrey,

Timothy Martin,

Shawki AreibiAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 14, Issue 3

Article No.: 16, Pages 1 - 28

https://doi.org/10.1145/3465373

Published: 12 August 2021 Publication History

Abstract

The ability to accurately and efficiently estimate the routability of a circuit based on its placement is one of the most challenging and difficult tasks in the Field Programmable Gate Array (FPGA) flow. In this article, we present a novel, deep learning framework based on a Convolutional Neural Network (CNN) model for predicting the routability of a placement. Since the performance of the CNN model is strongly dependent on the hyper-parameters selected for the model, we perform an exhaustive parameter tuning that significantly improves the model’s performance and we also avoid overfitting the model. We also incorporate the deep learning model into a state-of-the-art placement tool and show how the model can be used to (1) avoid costly, but futile, place-and-route iterations, and (2) improve the placer’s ability to produce routable placements for hard-to-route circuits using feedback based on routability estimates generated by the proposed model. The model is trained and evaluated using over 26K placement images derived from 372 benchmarks supplied by Xilinx Inc. We also explore several opportunities to further improve the reliability of the predictions made by the proposed DLRoute technique by splitting the model into two separate deep learning models for (a) global and (b) detailed placement during the optimization process. Experimental results show that the proposed framework achieves a routability prediction accuracy of 97% while exhibiting runtimes of only a few milliseconds.

References

[1]

Z. Abuowaimer, D. Maarouf, T. Martin, J. Foxcroft, G. Grewal, S. Areibi, and A. Vannelli. 2018. GPLace3.0: Routability-driven analytic placer for ultrascale FPGA architectures. ACM Trans. Des. Autom. Electron. Syst. 23, 5 (Oct. 2018), 66:1–66:33.

Digital Library

[2]

A. Al-Hyari and S. Areibi. 2017. Design space exploration of convolutional neural networks based on evolutionary algorithms. J. Computat. Vis. Imag. Syst. 3, 1 (Oct. 2017), 1–3.

[3]

A. Alhyari, A. Shamli, Z. Abuowaimer, G. Grewal, and S. Areibi. 2019. A deep learning framework to predict routability for FPGA circuit placement. In International Conference on Field Programmable Logic and Applications. 1–8.

[4]

S. Brown, J. Rose, and Z. Vranesic. 1993. A stochastic model to predict the routability of field programmable gate arrays. IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. 12, 12 (Dec. 1993), 1827–1838.

Digital Library

[5]

P. Chan, M. Schlag, and J. Zienr. 1993. On routability prediction for field programmable gate arrays. In Design Automation Conference. 326–330.

Digital Library

[6]

W. Chan, P. Ho, A. Kahng, and P. Saxena. 2017. Routability optimization for industrial designs at Sub-14nm process nodes using machine learning. In International Symposium on Physical Design. 15–21.

Digital Library

[7]

W. T. J. Chan, Y. Du, A. B. Kahng, S. Nath, and K. Samadi. 2016. BEOL stack-aware routability prediction from placement using data mining techniques. In International Conference on Computer Design (ICCD’16). 41–48.

[8]

B. Debowski, S. Areibi, G. Grewal, and J. Tempelman. 2012. A dynamic sampling framework for multi-class imbalanced data. In International Conference on Machine Learning and Applications. 113–118.

Digital Library

[9]

I. Goodfellow, Y. Bengio, and A. Courville. 2015. Deep Learning. The MIT Press, Cambridge, MA.

Digital Library

[10]

G. Grewal and S. Areibi. 2018. Guelph FPGA CAD Group. Retrieved from http://fpga.socs.uoguelph.ca/.

[11]

A. Gulli and S. Pal. 2017. Deep Learning with Keras. Packt Publishing Ltd.

Digital Library

[12]

PariVallal Kannan, Shankar Balachandran, and Dinesh Bhatia. 2001. fGREP - Fast generic routing demand estimation for placed FPGA circuits. In International Conference on Field-programmable Logic and Applications. Springer-Verlag, 37–47.

Digital Library

[13]

P. Kannan, S. Calachandran, and D. Bhatia. 2004. On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. VLSI 12, 4 (Apr. 2004), 381–385.

Digital Library

[14]

Guillaume Lemaître, Fernando Nogueira, and Christos K. Aridas. 2017. Imbalanced-learn: A Python toolbox to tackle the curse of imbalanced datasets in machine learning. J. Mach. Learn. Res. 18, 17 (2017), 1–5. Retrieved from http://jmlr.org/papers/v18/16-365.html.

Digital Library

[15]

W. Li, S. Dhar, and D. Pan. 2018. UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing. IEEE Trans. CAD Syst. 37, 4 (2018), 869–882.

Digital Library

[16]

Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, and Henry S. Sheng. 2002. Estimating routing congestion using probabilistic analysis. IEEE Trans. Comput.-aided Des. ICs Syst. 21, 2 (Jan. 2002).

[17]

D. Maarouf, A. Alhyari, Z. Abuowaimer, T. Martin, A. Gunter, G. Grewal, S. Areibi, and A. Vannelli. 2018. A machine-learning based congestion estimation for modern FPGAs. In IEEE International Conference on Field-programmable Logic and Applications. 427–434.

[18]

D. Marrouff, A. Shamli, T. Martin, G. Grewal, and S. Areibi. 2020. A deep-learning framework for predicting congestion during FPGA placement. In 30th International Conference on Field-programmable Logic and Applications. 138–144.

[19]

F. Pedregosa, G. Varoquaux, A. Gramfort, V. Michel, B. Thirion, O. Grisel, M. Blondel, P. Prettenhofer, R. Weiss, V. Dubourg, J. Vanderplas, A. Passos, D. Cournapeau, M. Brucher, M. Perrot, and E. Duchesnay. 2011. Scikit-learn: Machine learning in Python. J. Mach. Learn. Res. 12 (2011), 2825–2830.

Digital Library

[20]

C. Pui, G. Chen, W. Chow, K. Lam, P. Tu, H. Zhang, E. Young, and B. Yu. 2016. RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs. In International Conference on Computer-aided Design. 1–8.

Digital Library

[21]

C. Pui, G. Chen, Y. Ma, E. Young, and B. Yu. 2017. Clock-aware ultrascale FPGA placement with machine learning routability prediction. In IInternational Conference on Computer-aided Design. ACM, 929–936.

Digital Library

[22]

Z. Qi, Y. Cai, and Q. Zhou. 2014. Accurate prediction of detailed routing congestion using supervised data learning. In IEEE International Conference on Computer Design. 97–103.

[23]

A. Rahman, S. Oh, J. Lee, and K. Choi. 2017. Design space exploration of FPGA accelerators for convolutional neural networks. In Design, Automation & Test in Europe Conference (DATE’17). 1147–1152.

Digital Library

[24]

A. Tabrizi, N. Darav, L. Rakai, I. Bustany, A. Kennings, and L. Behjat. 2020. Eh? Predictor: A deep learning framework to identify detailed routing short violations from a placed netlist. IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. 39, 6 (June 2020), 1177–1190.

[25]

R. Glenn Wood and R. Rutenbar. 1997. FPGA Routing and routability estimation via boolean satisfiability. In International Symposium on FPGAs. 119–125.

Digital Library

[26]

Z. Xie, Y. Huang, G. Fang, H. Ren, S. Fang, Y. Chen, and J. Hu. 2018. RouteNet: Routability prediction for mixed-size designs using convolutional neural network. In International Conference on Computer-aided Design. 1–8.

Digital Library

[27]

Xilinx. 2016. ISPD 2016 Routability-Driven FPGA Placement Contest. Retrieved from http://www.ispd.cc/contests/16/ispd2016_contest.html.

Digital Library

[28]

S. Yang, A. Gayasen, C. Mulpuri, S. Reddy, and R. Aggarwal. 2016. Routability-driven FPGA placement contest. In International Symposium on Physical Design. 139–143.

Digital Library

[29]

D. Yeager, D. Chiu, and G. Lemieux. 2007. Congestion estimation and localization in FPGAs: A visual tool for interconnect prediction. In International Workshop on System Level Interconnect Prediction. ACM, 33–40.

Digital Library

[30]

C. Yu and Z. Zhang. 2019. Painting on placement: Forecasting routing congestion using conditional generative adversarial nets. In Design Automation Conference (DAC’19). 1–6.

Digital Library

[31]

J. Zhao, T. Liang, S. Sinha, and W. Zhang. 2019. Machine learning based routing congestion prediction in FPGA high-level synthesis. In Design, Automation and Test in Europe (DATE’19). 1130–1135.

[32]

Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai. 2015. An accurate detailed routing routability prediction model in placement. In Asia Symposium on Quality Electronic Design. 119–122.

[33]

Y. Zhuo, H. Li, and S. Mohanty. 2006. A congestion driven placement algorithm for FPGA synthesis. In International Conference on Field-programmable Logic and Applications. 683–686.

Cited By

Taj IFarooq U(2023)Towards Machine Learning-Based FPGA Backend Flow: Challenges and OpportunitiesElectronics10.3390/electronics1204093512:4(935)Online publication date: 13-Feb-2023
https://doi.org/10.3390/electronics12040935
Gunter AWilton S(2023)Reformulating the FPGA Routability Prediction Problem with Machine Learning2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00057(230-232)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00057
Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Show More Cited By

Index Terms

A Deep Learning Framework to Predict Routability for FPGA Circuit Placement

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 14, Issue 3

September 2021

137 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3472296

Editor:
Deming Chen
University of Illinois, Urbana-Champaign Urbana, USA

Issue’s Table of Contents

Copyright © 2021 Association for Computing Machinery.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 August 2021

Accepted: 01 May 2021

Revised: 01 January 2021

Received: 01 July 2020

Published in TRETS Volume 14, Issue 3

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Cited By

Taj IFarooq U(2023)Towards Machine Learning-Based FPGA Backend Flow: Challenges and OpportunitiesElectronics10.3390/electronics1204093512:4(935)Online publication date: 13-Feb-2023
https://doi.org/10.3390/electronics12040935
Gunter AWilton S(2023)Reformulating the FPGA Routability Prediction Problem with Machine Learning2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00057(230-232)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00057
Gunter AWilton S(2023)A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00016(63-74)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00016
Pal DDeng CUstun EYu CZhang Z(2022)Machine Learning for Agile FPGA DesignMachine Learning Applications in Electronic Design Automation10.1007/978-3-031-13074-8_16(471-504)Online publication date: 10-Aug-2022
https://doi.org/10.1007/978-3-031-13074-8_16

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